10-11-2008 10:48 AM
I have the following problem.
I tried the XUP reference design in Xilinx EDK 10.1 SP2. (http://www.xilinx.com/univ/xupv2p_demo_ref_designs.htm). I use XUPV2P platform with VDEC-1 add-on board.
If I merge the original edk design files into the EDK 10.1 project, the camera capture works until I change the opb_iic ip to the new xps_iic core. (So in my own project the PPC405 processor core, the plbv46 bus, plb2opb, proc_reset, clock_generator blocks are all up to date.) The video capture works with opb_iic controller, but not with the new xps_iic core. I would like to use this xps based core because it is free, and not an evaluate version like opb_iic.
I compared the opb_iic, xps_iic pdf files (along with the plbv46, opb_v2.0 bus parameters) supported by edk system, but only one difference was mentioned about the soft reset register configuration mechanism considering the xps_iic core. But as I examined, this feature was implemented in the original edk reference design files.
I would be verys appreciated if anybody could help me. Use anyone this xps_iic core with Digilent VDEC-1 board, or have any experiences with this ip core?
04-25-2010 01:51 PM
I am trying to implement that, using a PicoBlaze for VDEC-1 configuration (succesful) and streaming the video data to DDR memory (successful), but the trouble I am having now is related to the interlaced video as delivered by the ADV7183, because although it is interlaced, when I stream it down to the VGA output on the S3E kit, every time I reset the system the interlacing starts in a different line, making it difficult to figure out how exactly to do the de-interlacing- Any ideas on this?
So, so far I am able to get a static image (not yet refreshing) on a VGA display of some video Ifeed as input to the VDEC-1, all running on the S3E-500 StarterKit.
04-25-2010 10:28 PM
The ADV718x decoder outputs data in the BT656 (CCIR656 8 bit standard).
The stream includes a field of 4 bytes which is the encoding for the frame (odd/even) and other sync information. There are heaps of resources on the internet for this.
You can easily use this information to find the correct odd and even field to start your de-interlacing.
05-01-2010 01:28 AM
You might want to see this link:
If you read all the posts, you will find a lot of useful info and a working code for the XPS IIC core...
As for any experience with the VDEC, I recently managed to hack the VDEC example design which was for an NTSC camera to work with a PAL camera, (its just minor changes regarding the synch timings etc).
06-26-2010 01:46 AM
@ninjamafiakhan3 could you explain me a bit how did you hack vdec to work with PAL video system?
I'm trying to do so but with not much effect.
Basically I made my own design including the daugter board and:
- I work over special svga timing module to fit with PAL - I see video on screen but monitor is showing me error that I should change the timings (H: 31,2 kHz, V: 50Hz) signals.
I've create my own pixel_clock for this module but then there is nothing on the monitor - timing error again but this time H. frequency is OK (is divided accordingly the pixel_count and new pixel_clock) but V. frequency stays still on 50Hz so finnally they are not fit together.
Could you send your verilog files so I can compare where is my mistake?
12-17-2010 10:44 AM
Dont know if u already have VDEC1 and Spartan 3E working together. Can you please provide me with this code? I really need.