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Adventurer
Adventurer
1,870 Views
Registered: ‎02-13-2012

Problem about Digilent_Shared_Mem_Bus_Mux and axi cache

hello everyone

 

      I am encounting a problem aboout the axi cache and the mux_bus_share.

    

      When I just use the cellram.I can connect the cache to the cellram like this

axiram.jpg

 

But when use the mux_share_mem , I don't know how to do .

muxram.jpg

If I did this like when  there is only cellram.

 

The xps report error EDK:3759 - AddresGen MHS Error You have a non cacheable core(Digilent_Shared_Mem_Bus_Mux->C_FLASH_BASEADDR) on M_AXI_DC interface(axi_interconnect_0). Address Generator does not support this case


Can I still use the Digilent_SharedMem_Bus_Mux ip core if I want to use the cache?

 

Thanks for your reply anyway.

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1 Reply
Visitor juansolsona
Visitor
1,849 Views
Registered: ‎11-01-2011

Re: Problem about Digilent_Shared_Mem_Bus_Mux and axi cache

I guess that your trouble is that the mux_bus_share is an axi lite peripheral, but the cache must be filled on bursts, and axi lite does not allow it.

 

On the other hand, I would like to ask you how did you manage to get an AXI controller for the Micron cellram? Did you generate it using the MIG wizard?

 

Kind regards

Juan

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