cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
meta1360
Explorer
Explorer
10,712 Views
Registered: ‎01-29-2014

Problem in generating BSP in SDK

Jump to solution

Hi all,

 

I am using Vivado 2015.2  I export my design to SDK and lunch it then I want to make a new project but when I fill the application project windows and push next and choose an empty application or hello word I go this error  

please look at the picture attached here 

 

Please help me out of this problem I downgraded my software to 2014.4 but I got the same problem and it is very frustrating and I really appreciate all your help in advance . I also attached the log file in cases it is needded. 

 

Meysam

 

12:00:24 ERROR : Internal error: Num intr inputs 2 not the same as length of ::hsi::utils::get_interrupt_sources 1 hsi_error
can't read "source_name(1)": no such element in array
[Hsi 55-1545] Problem running tcl command ::sw_intc_v3_3::generate : can't read "source_name(1)": no such element in array
while executing
"string compare -nocase $source_name($i) "system""
("foreach" body line 34)
invoked from within
"foreach periph $periphs {
# Get the edk based name of peripheral for printing redefines
set periph_ip_name [common::get_property NAME..."
(procedure "xredefine_intc" line 10)
invoked from within
"xredefine_intc $drv_handle $file_handle"
(procedure "xdefine_canonical_xpars" line 71)
invoked from within
"xdefine_canonical_xpars $drv_handle "xparameters.h" "Intc" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C..."
(procedure "::sw_intc_v3_3::generate" line 57)
invoked from within
"::sw_intc_v3_3::generate microblaze_0_axi_intc"
[Hsi 55-1442] Error(s) while running TCL procedure generate()
12:00:24 ERROR : Error generating bsp sources: Failed to generate BSP.

Screenshot-8.png
0 Kudos
1 Solution

Accepted Solutions
achutha
Xilinx Employee
Xilinx Employee
19,430 Views
Registered: ‎07-01-2010

@meta1360

 

The issue is with your block design interrupt connection.In which you have not connected the other pin of concat IP as you only have 1 interrupt.

Double clicking on concat IP and set the width to 1 will resolve the issue.After the changing the settings and validating the design you should see similar to modified snippet.

 

concat.PNG

 

Modified snippet:

 

Concat_fix.PNG

Hope this helps.

 

-Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------

View solution in original post

9 Replies
achutha
Xilinx Employee
Xilinx Employee
10,673 Views
Registered: ‎07-01-2010

Can you try using the zynq pre-defined hardware inSDK to understand if this is your exported HW issue or anything else?

Please share the block design or hdf to replicate the issue.

 

-Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
meta1360
Explorer
Explorer
10,671 Views
Registered: ‎01-29-2014

Thanks Achutha for your reply. 

 

Yes this issue is because of my design because as you said when I try it with pre-defined design it works and I can have a new project.   

I attached my blobk design (bd file) and hdf file here

should you need more information please let me know.  

thanks for spending time on this

 

Meysam 

0 Kudos
sampatd
Scholar
Scholar
10,651 Views
Registered: ‎09-05-2011
I got the same error in SDK 2015.2 using the hdf you attached. I could not check the block the design as you might have some custom IPs.

Can you post a screenshot of your block diagram?

Do you receive any critical warnings when generating the bitstream in Vivado?
0 Kudos
meta1360
Explorer
Explorer
10,649 Views
Registered: ‎01-29-2014

thank you so much for your reply

 

Can you post a screenshot of your block diagram?

 

I attached the photo of my design, yes I have a customized IP called BTM if it is helpful I can attach that IP as well.  

 

Do you receive any critical warnings when generating the bitstream in Vivado?

 

in that step no there is not any critical warning but in implementation, I got some which are about set_property for some inputs and outputs which do not exist anymore and I think it is not a big deal. 

 

 

I really appreciate all your help. 

 

Regards,

Meysam

 

 

0 Kudos
sampatd
Scholar
Scholar
10,645 Views
Registered: ‎09-05-2011

If possible can you archive the Vivado Project and attach it here?  I can take a look.

 

Otherwise, I can send you an FTP link where you can attach the archived project securely.

0 Kudos
achutha
Xilinx Employee
Xilinx Employee
10,633 Views
Registered: ‎07-01-2010

@meta1360

 

The issue you are seeing seems to be similar to the issue discussed in the answer record http://www.xilinx.com/support/answers/60969.html

 

It looks like you have custom IP in your design and so i was not able to review the block design using the BD shared.

 

As suggested by Sampat please archive the Vivado project and share it with us.

 

-Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
meta1360
Explorer
Explorer
10,622 Views
Registered: ‎01-29-2014

I could not attache here please find it in 

 

http://speedy.sh/TWhSG/MB-BTM-Multiple-RANK.zip

 

thanks for your help. 

0 Kudos
achutha
Xilinx Employee
Xilinx Employee
19,431 Views
Registered: ‎07-01-2010

@meta1360

 

The issue is with your block design interrupt connection.In which you have not connected the other pin of concat IP as you only have 1 interrupt.

Double clicking on concat IP and set the width to 1 will resolve the issue.After the changing the settings and validating the design you should see similar to modified snippet.

 

concat.PNG

 

Modified snippet:

 

Concat_fix.PNG

Hope this helps.

 

-Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------

View solution in original post

meta1360
Explorer
Explorer
10,601 Views
Registered: ‎01-29-2014
thanks for your help, it works.
0 Kudos