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Visitor soniya_nn
Visitor
7,793 Views
Registered: ‎09-28-2012

Problem in user_logic simulation

Hi,

I am a beginner using EDK. I have a floating point divider module and  want to use it as a  component in my user_logic.vhd file (in a PowerPC PLB system). My_fp_divider module is  added to .pao file of my project now like this: 

 

lib divider_v1_00_a my_fp_divider vhdl
lib divider_v1_00_a user_logic vhdl
lib divider_v1_00_a divider vhdl

 

I don't know what is wrong with my user_logic code since in my simulation Bus2IP_WrCE signal doesn't change at all.

Here is my C++ and VHDL code and simulation picture in modelsim10. 

Thanks in advance

 

user_logic.vhd:

 

component my_divider
   port(
      
      x : in STD_LOGIC_VECTOR (31 downto 0);
		y : in STD_LOGIC_VECTOR (31 downto 0);
		z : out STD_LOGIC_VECTOR (31 downto 0)
		);
end component;

	signal a,b,c : std_logic_vector (31 downto 0) ;
	signal count : std_logic_vector (1 downto 0 ) ;
	signal ready : std_logic ;

begin

  --USER logic implementation added here
  
  divider_0 : my_divider
  port map (
    x => a ,
    y => b,
    z => c
  );

	p0 : process(Bus2IP_Clk)
	begin
  if rising_edge(Bus2IP_Clk) then
		IP2Bus_WrAck <= '0';
      IP2Bus_RdAck <= '0';
		
    if (Bus2IP_Reset = '1') then
      IP2Bus_WrAck <= '0';
      IP2Bus_RdAck <= '0';
		count <= (others => '0' ) ;
      a <= (others => '0');
		b <= (others => '0');
		c <= (others => '0');
		ready <= '0' ;
    elsif (Bus2IP_WrCE(0) = '1') then 
      case count is
			when "00" => 
				a <= Bus2IP_Data ;
				count <= count + 1 ;
				ready <= '0' ;
			when "01" =>  
				b <= Bus2IP_Data ;
				count <= ( others => '0' ) ;
				ready <= '1' ;
			when others  => null ;
		end case ;
		
      IP2Bus_RdAck <= '1' ;
		
    elsif (Bus2IP_RdCE(0) = '1') and ready = '1' then
		IP2Bus_Data <= c ;
      IP2Bus_WrAck <= '1' ;
    end if;
  end if;
end process p0;
 
IP2Bus_Error <= '0';
  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  
end IMP;

 c++ code:

#include <XPARAMETERS.H>
#include <xio.h>
int main()
{
int a = 7;
int b = 2 ;
XIo_Out32(XPAR_DIVIDER_0_BASEADDR , a );
// XIo_Out32(XPAR_DIVIDER_0_BASEADDR ,b);
// b = XIo_In32(0x0000A000);
return 0;
}

 

sim_result.jpg
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11 Replies
Teacher hgleamon1
Teacher
7,778 Views
Registered: ‎11-14-2011

Re: Problem in user_logic simulation

When you simulate, can you see the write activity from the PowerPC and on the PLB? Is the PLB correctly connected to your custom IP?

 

Your divider module is called "my_divider" in the attached code but "my_fp_divider" in your library. These should be consistent.

 

Secondly, although unrelated to your problem, I think you have your Read and Write Acknowledges the wrong way round.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor soniya_nn
Visitor
7,774 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

Thanks for your attention. My module's entity name is my_divider but the file name is my_FP_divider, must they be the same?

Yes the peripheral is connected to powerpc with plb bus and is addressed correctly.

I'm not sure to check which signals, but some i checked for plb bus dont have activity.

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Teacher hgleamon1
Teacher
7,770 Views
Registered: ‎11-14-2011

Re: Problem in user_logic simulation

There should be SOME PLB activity almost all of the time. Look at the PPC module in simulation, go through it clock by clock cycle if necessary.

 

How do you know your PPC is actually executing code in the simulation? I suspect the problem lies in the bigger picture, rather than just this piece of VHDL.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor soniya_nn
Visitor
7,763 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

I thought something was wrong with my vhdl code.

here is some bigger pictures, one is BRAM's signals which i think is not working correctly.

sim_result.jpg

 

bram_result.jpg

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Visitor soniya_nn
Visitor
7,742 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

Something that I recently understand is that one timing constraint is not met in my system. Can this issue cause the problem?

time_constraint_not_met.jpg

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Teacher hgleamon1
Teacher
7,737 Views
Registered: ‎11-14-2011

Re: Problem in user_logic simulation

Only if you are doing post-PAR simulation.

 

The issue seems to be centred on why you seem to have no PLB activity. Are you sure your ELF file is included in your simulation?

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor soniya_nn
Visitor
7,733 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

Yes, I checked .mem files in simulation folder, and they are initialized.

Here is a sample attached .mem file:

Am I right?

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Teacher hgleamon1
Teacher
7,721 Views
Registered: ‎11-14-2011

Re: Problem in user_logic simulation

It seems OK.

 

Can you successfully simulate your user_logic outside of a system-wide simulation, so that we may eliminate the user_logic module as a possible fault?

 

Can you step through your system-wide code in the SDK debugger and see that values are written and returned? You may need to put some debug lines in your software to really see the benefit.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor soniya_nn
Visitor
7,712 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

As you recommended, I simulated the user_logic and I think it's OK, at least it responded to testbench read and write signals.

I thought the problem is something related to BRAM (because of no activity on BRAM signals), so I changed the linker script from:

scri1.jpg

To this one:

scri2.jpg

And I saw that instruction memory is OK (I think, at least has activity) but Data memory has no activity. Here is simulation:

data_mem_not_act.jpg

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Teacher hgleamon1
Teacher
2,617 Views
Registered: ‎11-14-2011

Re: Problem in user_logic simulation

Well it looks like you are on the right track. I have never used a PPC design, so I cannot say for certain exactly where your data and instruction should be placed. I also don't know where your heap and stack should be placed.

 

Further, without knowledge of your complete system and how it is connected, I can't say how your BRAMs should be connected and filled. Perhaps some further experimenting with the BRAMs in the linker script will help .. ?

 

Regards,

 

Howard.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Highlighted
Visitor soniya_nn
Visitor
2,614 Views
Registered: ‎09-28-2012

Re: Problem in user_logic simulation

OK, thank you very much for your help and contributing.
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