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Visitor ruizmartinez
Visitor
4,757 Views
Registered: ‎10-28-2009

Problem in using Modelsim SE 6.5c with EDK 11.1

Hi,

 

i have this problem with the Simulation libraries compilation

 

____ ____

/ /\/ /

/___/ \ / VENDOR : Xilinx Inc.

\ \ \/ VERSION : 11.1 (L.33)

\ \ APPLICATION : C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe

/ / CONTENTS : Compilation Log

/___/ /\ FILENAME : compxlib.log

\ \ / \

\___\/\___\

Release 11.1 - C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe L.33 (nt)

Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

Processing command line ...

Reading the compxlib configuration file - 'compxlib.cfg' ...

Library Source Paths => 'C:/Xilinx/11.1/ISE'

Current Working Directory => 'C:\Documents and Settings\ruizmartinez\My Documents\RuizMartinez\ISE projects\Prueba1'

Compilation Mode = FAST

Execute Mode = ON

Scheduling library installation & compilation for architectures: virtex5

Scheduling library installation & compilation for libraries: simprim unisim xilinxcorelib edk

Signature:-

------------------------------------------------------------------------------

C:\Xilinx\11.1\ISE\bin\nt\unwrapped\compxlib.exe -s mti_se -l vhdl -p C:/ModelSimSE65/win32 -arch virtex5 -lib unisim -lib simprim -lib xilinxcorelib -lib edk -exclude_deprecated -intstyle ise

------------------------------------------------------------------------------

Setting up the simulator 'mti_se' for compilation ...

Setting up the source libraries for simulator 'mti_se' ...

Retrieving the .pao files for EDK library ...

Building the library hierarchies from the .pao files for EDK library ...

Assigning the netlist files to the hierarchies for EDK library ...

Compiling Xilinx HDL Libraries for 'mti_se' simulator

Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22 2009

Language => 'vhdl,verilog'

Output directory => 'C:\Xilinx\11.1\ISE'

Library verilog.secureip will not be compiled, because precompiled info is up to date.

compxlib[verilog.secureip]: 0 error(s), 0 warning(s), 12.50 % complete

Library vhdl.unisim will be compiled, because precompiled info is outdated.

--> Compiling vhdl.unisim library ...

> vhdl.unisim library compiled from C:/Xilinx/11.1/ISE/vhdl/src/unisims

> vhdl.unisim library compiled to C:\Xilinx\11.1\ISE\vhdl\mti_se/unisim

==============================================================================

Modifying modelsim.ini

 

p, li { white-space: pre-wrap; }

 

==============================================================================

> Log file 'C:\Xilinx\11.1\ISE\vhdl\mti_se/unisim/.cxl.vhdl.unisim.unisim.nt.log' generated

 

Library vhdl.unisim:vhdl.unimacro will be compiled, because precompiled info is outdated.

--> Compiling vhdl.unisim:vhdl.unimacro library ...

> vhdl.unisim:vhdl.unimacro library compiled from C:/Xilinx/11.1/ISE/vhdl/src/unimacro

> vhdl.unisim:vhdl.unimacro library compiled to C:\Xilinx\11.1\ISE\vhdl\mti_se/unimacro

==============================================================================

Modifying modelsim.ini

 

Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22 2009

-- Loading package standard

-- Loading package std_logic_1164

-- Loading package numeric_std

-- Loading package std_logic_arith

-- Loading package std_logic_unsigned

-- Loading package vcomponents

-- Loading package textio

-- Compiling entity addmacc_macro

-- Compiling architecture addmacc of addmacc_macro

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(296): DSP48E_1: DSP48E1

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(296): (vcom-1141) Identifier "dsp48e1" does not identify a component declaration.

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(361): DSP48E_2: DSP48A1

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(361): (vcom-1141) Identifier "dsp48a1" does not identify a component declaration.

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(405): end addmacc;

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(405): VHDL Compiler exiting

 

 

 

 

I don't know if the spaces in the directory is the problem ....

 

Thank you very much in advance for your help ...

 

Emilio

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2 Replies
Xilinx Employee
Xilinx Employee
4,755 Views
Registered: ‎08-02-2007

Re: Problem in using Modelsim SE 6.5c with EDK 11.1

Hi,

 

I still think you have the working directory on the Desktop, so it is having spaces in the project location.

 

Please keep the output directory of the compiled libraries in another location without any spaces.

 

Thanks.

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Visitor ruizmartinez
Visitor
4,753 Views
Registered: ‎10-28-2009

Re: Problem in using Modelsim SE 6.5c with EDK 11.1

Hi,

 

thanks for your answer, but it is still not working..... i've changed the current working directory to

 

Current Working Directory => 'C:\pp\lolo'

 

 and the output directory is >>>

 

Output directory => 'C:\Xilinx\11.1\ISE'

 

I still have the same error

 

p, li { white-space: pre-wrap; }

 

==============================================================================

> Log file 'C:\Xilinx\11.1\ISE\vhdl\mti_se/unisim/.cxl.vhdl.unisim.unisim.nt.log' generated

 

Library vhdl.unisim:vhdl.unimacro will be compiled, because precompiled info is outdated.

--> Compiling vhdl.unisim:vhdl.unimacro library ...

> vhdl.unisim:vhdl.unimacro library compiled from C:/Xilinx/11.1/ISE/vhdl/src/unimacro

> vhdl.unisim:vhdl.unimacro library compiled to C:\Xilinx\11.1\ISE\vhdl\mti_se/unimacro

==============================================================================

Modifying modelsim.ini

 

Model Technology ModelSim SE vcom 6.5 Compiler 2009.01 Jan 22 2009

-- Loading package standard

-- Loading package std_logic_1164

-- Loading package numeric_std

-- Loading package std_logic_arith

-- Loading package std_logic_unsigned

-- Loading package vcomponents

-- Loading package textio

-- Compiling entity addmacc_macro

-- Compiling architecture addmacc of addmacc_macro

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(296): DSP48E_1: DSP48E1

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(296): (vcom-1141) Identifier "dsp48e1" does not identify a component declaration.

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(361): DSP48E_2: DSP48A1

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(361): (vcom-1141) Identifier "dsp48a1" does not identify a component declaration.

###### C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(405): end addmacc;

** Error: C:/Xilinx/11.1/ISE/vhdl/src/unimacro/ADDMACC_MACRO.vhd(405): VHDL Compiler exiting

 

 

==============================================================================

> Log file 'C:\Xilinx\11.1\ISE\vhdl\mti_se/unimacro/.cxl.vhdl.unimacro.unimacro.nt.log' generated

compxlib[vhdl.unisim:vhdl.unimacro]: 1 error(s), 0 warning(s)

 

INFO:Compxlib:370 - Please refer to the compile log file 'C:\Xilinx\11.1\ISE\vhdl\mti_se/unimacro/.cxl.vhdl.unimacro.unimacro.nt.log' for details of compilation error(s).

 

 

Library vhdl.unisim:vhdl.secureip_vhdl_unisim will not be compiled, because precompiled info is up to date.

compxlib[vhdl.unisim:vhdl.secureip_vhdl_unisim]: 0 error(s), 0 warning(s)

 

compxlib[vhdl.unisim]: 1 error(s), 0 warning(s), 25.00 % complete

 

 

 

 

thank you very much for your help....

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