UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
3,115 Views
Registered: ‎04-23-2013

Problem w/ SPI CPHA setting

Hello,

 

I am trying to interface to an SPI device in SPI Mode 1 (CPOL=0, CPHA=1)

Please see attachment.

 

I am setting this:

InitStatus = XSpiPs_SetOptions(&SpiInstance,
XSPIPS_MASTER_OPTION | XSPIPS_CLK_PHASE_1_OPTION | XSPIPS_FORCE_SSELECT_OPTION);

 

The problem is that the clock is high when CS goes low and then glitches low then up very quickly.

It should be low when CS asserts.

 

Apparently this counts as a clock because there are 16 including this one.

However, the data is not shifted and is one bit late thereafter.

 

Am I setting the options wrong?

 

Thanks,

Emmett

ADS1018 SPI .png
SPI_CPHA1_CPOL0.jpg
SPI_CPHA1_CPOL0_zoom.jpg
0 Kudos
6 Replies
Explorer
Explorer
3,111 Views
Registered: ‎04-23-2013

Re: Problem w/ SPI CPHA setting

I miscounted, so apparently the glitch is not counted as a clock.

It looks like the problem is that SCLK goes high when CS de-asserts.

 

Also, why the ~1.6ms delay for CS de-assertion?

SPI_CPHA1_CPOL0_zoomout.jpg
0 Kudos
Scholar ericv
Scholar
3,084 Views
Registered: ‎04-13-2015

Re: Problem w/ SPI CPHA setting

@emmettbradford

 

This may not be much reassurance to you, but you are not alone seeing these hick-ups with the CS & clock signals.

Every time I saw them and analyzed, they look to me as they didn't matter after all.

 

For the 1 bit delay, are you sending or receiving?

And what is the peripheral?

 

I agree that with CPOL=0 the clock should be held low when CS is high, but my understanding is the nomenclature is only valid when CS is low and it's simply a way to say the data is sampled on the low-to-high transition with CPHA=0 and high to low with CPHA=1... and the data changes on the opposite transition.

When you look at most docs, the clock and all other signals are shown with "gray shade" outside CS low.

 

For the deassertion delay, is CS control is set in auto or manual mode?

If it's in manual mode such a large delay is very likely as the CS is set high or low by software.

 

Regards

 

 

0 Kudos
Highlighted
Explorer
Explorer
3,059 Views
Registered: ‎04-23-2013

Re: Problem w/ SPI CPHA setting

Hi Eric.

Thanks for your reply.

 

The peripheral is TI ADS1018.

I am sending a 16 bit config word and receiving the last ADC result.

 

I am using the XSPIPS_FORCE_SSELECT_OPTION thinking that would be faster.

I'll try w/ software de-assert..

 

I also saw examples of manually setting delays, but have not played with those yet.

Maybe there are some bad defaults.

 

Thanks,

Emmett

 

Here is my periodic transfer code:

 

// Send the command, Get the ADC reading
SpiTxBuff[0] = (u8)((ADCConfig>>8) & 0x00FF);
SpiTxBuff[1] = (u8)((ADCConfig) & 0x00FF);
XSpiPs_SetSlaveSelect(&SpiInstance, 1); // Select slave 1
// XSpiPs_Transfer(&SpiInstance, &SpiTxBuff[0], &SpiRxBuff[0], 2);
XSpiPs_PolledTransfer(&SpiInstance, &SpiTxBuff[0], &SpiRxBuff[0], 2);
ADCResult=SpiRxBuff[0]<<8;
ADCResult+=SpiRxBuff[1];

 

Below is my init code:

 

// Initialize SPI Device
SpiConfig = XSpiPs_LookupConfig(XPAR_PS7_SPI_0_DEVICE_ID);
if (NULL == SpiConfig) return XST_FAILURE;

InitStatus = XSpiPs_CfgInitialize(&SpiInstance, SpiConfig, SpiConfig->BaseAddress);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

XSpiPs_Reset(&SpiInstance); // necessary??

SpiConfig->InputClockHz = XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ;

// Set the clock pre-scaler to 167MHz / 256 ~= 651kHz
InitStatus = XSpiPs_SetClkPrescaler(&SpiInstance, XSPIPS_CLK_PRESCALE_256);

// Perform a self-test to ensure that the hardware was built correctly. This defaults all options
InitStatus = XSpiPs_SelfTest(&SpiInstance);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the SPI device as a master, manual SS and auto start.
InitStatus = XSpiPs_SetOptions(&SpiInstance,
XSPIPS_MASTER_OPTION | XSPIPS_CLK_PHASE_1_OPTION | XSPIPS_FORCE_SSELECT_OPTION);
// XSPIPS_MASTER_OPTION | XSPIPS_CLK_ACTIVE_LOW_OPTION | XSPIPS_FORCE_SSELECT_OPTION);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the clock pre-scaler to 167MHz / 256 ~= 651kHz
InitStatus = XSpiPs_SetClkPrescaler(&SpiInstance, XSPIPS_CLK_PRESCALE_256);
if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Set the transfer delays = u8 DelayNss, u8 DelayBtwn, u8 DelayAfter, u8 DelayInit
// InitStatus = XSpiPs_SetDelays(&SpiInstance, 1, 2, 3, 4);
// if (InitStatus != XST_SUCCESS) return XST_FAILURE;

// Enable the SPI device
XSpiPs_Enable(&SpiInstance);

0 Kudos
Explorer
Explorer
3,056 Views
Registered: ‎04-23-2013

Re: Problem w/ SPI CPHA setting

Here it is w/o the XSPIPS_FORCE_SSELECT_OPTION.

It is much better and probably SPI-legal, but I don't like the clock transitions near the CS assertions.

SPI_CPHA1_CPOL0_noFORCE.jpg
SPI_CPHA1_CPOL0_noFORCE_zoom.jpg
0 Kudos
Scholar ericv
Scholar
3,046 Views
Registered: ‎04-13-2015

Re: Problem w/ SPI CPHA setting

@emmettbradford

 

I currently don't have access to everything I would need to double check.

But a quick thing you could try is to change CPOL & CPHA

You are currently using CPOL=0, CPHA=1

You should try with CPOL=1, CPHA=0 instead.

This may remove the clock going to zero during that initial CS glitch as the inactive clock is high, and the sampling / output phases are the same transitions as what you are currently using.

Fingers crossed the the ADC only reacts to the low->high transitions to put the next bit on the bus, irrelevant of the initial clock level.

 

Regards

Explorer
Explorer
2,720 Views
Registered: ‎04-23-2013

Re: Problem w/ SPI CPHA setting

This turned out to be a pin assignment issue in constraints.

Thanks for your help, Eric.

Emmett

0 Kudos