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samboy786
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Registered: ‎11-23-2011

Problem with PCI implementation on ML510 board

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I am trying to injterface a PCI (5V) card with  ML510 board using PPC440@125MHz. I am stuck with the interrrupt controller core. I am using ISE 13.2 design suite. When I am importing the mhs file to SDK, it fails to generate the corresponding libraries files for interrupt controller ( xps_intc) giving the following error message :

 

Staging source files.
Running DRCs.
MFS DRC ...

Running generate.
ERROR:EDK - intc () - Internal error: Number of interrupt inputs on xps_intc_0
(2) is not the same as length of total number of interrupt sources (6). If
any interrupt source is a vector then libgen does not support this use case
MFS generate ...

ERROR:EDK:3416 - Error(s) while running TCL procedure generate().

 

I have tried c

hecking number of interrupt inputs on intc . It is 6 in mhs file while the mpd shows only two. I have also tried changing the C_NUM_INTR_INPUTS in the original mpd file from 2 to 6. I have changed these parameters in the hdl files ( intc_core and xps_intc) as well. But nothing seems to produce any change in the output. I am getting the same error all over the time. 

I am attaching the MHS file for reference. Plz help asap :( :(

 

PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO_pin, DIR = IO, VEC = [0:3]
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN_pin, DIR = O
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN_pin, DIR = O
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN_pin, DIR = O
PORT fpga_0_FLASH_Mem_ADV_LDN_pin = fpga_0_FLASH_Mem_ADV_LDN_pin, DIR = O
PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ_pin, DIR = IO, VEC = [0:15]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CE_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_ODT_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_RAS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CAS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_WE_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Addr_pin, DIR = O, VEC = [13:0]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DM_pin, DIR = O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_n_pin = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_n_pin, DIR = IO, VEC = [7:0]
PORT fpga_0_pci_arbiter_0_PCI_Req_n_pin = fpga_0_pci_arbiter_0_PCI_Req_n_pin_vslice_1_5_concat, DIR = I, VEC = [1:5]
PORT fpga_0_pci_arbiter_0_PCI_Gnt_n_pin = fpga_0_pci_arbiter_0_PCI_Gnt_n_pin_vslice_1_5_concat, DIR = O, VEC = [1:5]
PORT fpga_0_PCI32_BRIDGE_AD_pin = fpga_0_PCI32_BRIDGE_AD_pin, DIR = IO, VEC = [31:0]
PORT fpga_0_PCI32_BRIDGE_CBE_pin = fpga_0_PCI32_BRIDGE_CBE_pin, DIR = IO, VEC = [3:0]
PORT fpga_0_PCI32_BRIDGE_PAR_pin = fpga_0_PCI32_BRIDGE_PAR_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_FRAME_N_pin = fpga_0_PCI32_BRIDGE_FRAME_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_TRDY_N_pin = fpga_0_PCI32_BRIDGE_TRDY_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_IRDY_N_pin = fpga_0_PCI32_BRIDGE_IRDY_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_STOP_N_pin = fpga_0_PCI32_BRIDGE_STOP_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_DEVSEL_N_pin = fpga_0_PCI32_BRIDGE_DEVSEL_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_PERR_N_pin = fpga_0_PCI32_BRIDGE_PERR_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_SERR_N_pin = fpga_0_PCI32_BRIDGE_SERR_N_pin, DIR = IO
PORT fpga_0_PCI32_BRIDGE_PCI_INTA_pin = fpga_0_PCI32_BRIDGE_PCI_INTA_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_PCI32_BRIDGE_PCI_INTB_pin = fpga_0_PCI32_BRIDGE_PCI_INTB_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_PCI32_BRIDGE_PCI_INTC_pin = fpga_0_PCI32_BRIDGE_PCI_INTC_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_PCI32_BRIDGE_PCI_INTD_pin = fpga_0_PCI32_BRIDGE_PCI_INTD_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_PCI32_BRIDGE_PCI_SBR_INT_pin = fpga_0_PCI32_BRIDGE_PCI_SBR_INT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = MEDIUM
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_OUT0_pin = clk_33_3333MHz, DIR = O
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_OUT1_pin = clk_33_3333MHz, DIR = O
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_OUT3_pin = clk_33_3333MHz, DIR = O
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_OUT4_pin = clk_33_3333MHz, DIR = O
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_OUT5_pin = clk_33_3333MHz, DIR = O
PORT fpga_0_PCI32_BRIDGE_PCI_CLK_FB_pin = pci_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 33333333
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT fpga_0_ORGate_1_Res_SBR_PWG_RSM_RSTJ_pin = fpga_0_ORGate_1_Res_pin, DIR = O
PORT fpga_0_ORGate_1_Res_PCI_reset_all_pin = fpga_0_ORGate_1_Res_pin, DIR = O


BEGIN ppc440_virtex5
PARAMETER INSTANCE = ppc440_0
PARAMETER C_IDCR_BASEADDR = 0b0000000000
PARAMETER C_IDCR_HIGHADDR = 0b0011111111
PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 2
PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
PARAMETER HW_VER = 1.01.a
PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x00000000
PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0x1fffffff
PARAMETER C_SPLB0_RNG1_MPLB_BASEADDR = 0x80000000
PARAMETER C_SPLB0_RNG1_MPLB_HIGHADDR = 0xffffffff
BUS_INTERFACE MPLB = plb_v46_0
BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
BUS_INTERFACE RESETPPC = ppc_reset_bus
PORT CPMC440CLK = clk_125_0000MHzPLL0
PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
PORT CPMINTERCONNECTCLKNTO1 = net_vcc
PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
END

BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_0
PARAMETER C_DCR_INTFCE = 0
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_1
PARAMETER C_SPLB_NATIVE_DWIDTH = 64
PARAMETER C_SPLB_SUPPORT_BURSTS = 1
PARAMETER C_SPLB_P2P = 0
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff8000
PARAMETER C_HIGHADDR = 0xffffffff
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT RX = fpga_0_RS232_Uart_1_RX_pin
PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO_pin
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TWC_PS_MEM_0 = 110000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0xe8000000
PARAMETER C_MEM0_HIGHADDR = 0xe9ffffff
BUS_INTERFACE SPLB = plb_v46_0
PORT RdClk = clk_125_0000MHzPLL0_ADJUST
PORT Mem_A = 0b0000000 & fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat & 0b0
PORT Mem_CEN = fpga_0_FLASH_Mem_CEN_pin
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
PORT Mem_ADV_LDN = fpga_0_FLASH_Mem_ADV_LDN_pin
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END

BEGIN mpmc
PARAMETER INSTANCE = DDR2_SDRAM_DIMM1
PARAMETER C_NUM_PORTS = 1
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y4
PARAMETER C_MEM_PARTNO = WD2RE512X809-667D
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_MEM_CLK_WIDTH = 1
PARAMETER C_MEM_ODT_WIDTH = 1
PARAMETER C_MEM_CE_WIDTH = 1
PARAMETER C_MEM_CS_N_WIDTH = 1
PARAMETER C_MEM_DATA_WIDTH = 64
PARAMETER C_DDR2_DQSN_ENABLE = 1
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER HW_VER = 6.04.a
PARAMETER C_MPMC_BASEADDR = 0x00000000
PARAMETER C_MPMC_HIGHADDR = 0x1fffffff
BUS_INTERFACE SPLB0 = plb_v46_0
PORT MPMC_Clk0 = clk_125_0000MHzPLL0_ADJUST
PORT MPMC_Clk0_DIV2 = clk_62_5000MHzPLL0_ADJUST
PORT MPMC_Clk90 = clk_125_0000MHz90PLL0_ADJUST
PORT MPMC_Clk_200MHz = clk_200_0000MHz
PORT MPMC_Rst = sys_periph_reset
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_pin
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Clk_n_pin
PORT DDR2_CE = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CE_pin
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CS_n_pin
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DIMM1_DDR2_ODT_pin
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_RAS_n_pin
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_CAS_n_pin
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_WE_n_pin
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DIMM1_DDR2_BankAddr_pin
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DIMM1_DDR2_Addr_pin
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQ_pin
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DM_pin
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_pin
PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DIMM1_DDR2_DQS_n_pin
END

BEGIN pci_arbiter
PARAMETER INSTANCE = pci_arbiter_0
PARAMETER C_NUM_PCI_MSTRS = 6
PARAMETER HW_VER = 1.00.a
PORT PCI_Clk = pci_feedback_s
PORT PCI_Rst_n = net_vcc
PORT PCI_Req_n = fpga_0_pci_arbiter_0_PCI_Req_n_pin_vslice_0_0_concat & fpga_0_pci_arbiter_0_PCI_Req_n_pin_vslice_1_5_concat
PORT PCI_Gnt_n = fpga_0_pci_arbiter_0_PCI_Gnt_n_pin_vslice_0_0_concat & fpga_0_pci_arbiter_0_PCI_Gnt_n_pin_vslice_1_5_concat
PORT PCI_Frame_n = net_bsbassign0
PORT PCI_Irdy_n = net_bsbassign2
END

BEGIN plbv46_pci
PARAMETER INSTANCE = PCI32_BRIDGE
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y7-IDELAYCTRL_X2Y8
PARAMETER C_INCLUDE_INTR_A_BUF = 0
PARAMETER C_INCLUDE_REQ_N_BUF = 0
PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 16
PARAMETER C_IPIF2PCI_FIFO_ABUS_WIDTH = 9
PARAMETER C_PCI2IPIF_FIFO_ABUS_WIDTH = 9
PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 3000
PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 1
PARAMETER C_IPIFBAR_NUM = 2
PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
PARAMETER C_IPIF_SPACETYPE_0 = 1
PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
PARAMETER C_IPIF_SPACETYPE_1 = 0
PARAMETER C_PCIBAR_NUM = 1
PARAMETER C_PCIBAR2IPIFBAR_0 = 0x00000000
PARAMETER C_PCIBAR_LEN_0 = 29
PARAMETER C_DEVICE_ID = 0x0510
PARAMETER C_VENDOR_ID = 0x10EE
PARAMETER C_CLASS_CODE = 0x060000
PARAMETER C_REV_ID = 0x1A
PARAMETER C_SUBSYSTEM_ID = 0x0510
PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x10EE
PARAMETER C_MAX_LAT = 0x54
PARAMETER C_MIN_GNT = 0x32
PARAMETER C_NUM_IDSEL = 16
PARAMETER C_BRIDGE_IDSEL_ADDR_BIT = 16
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x85e00000
PARAMETER C_HIGHADDR = 0x85e0ffff
PARAMETER C_IPIFBAR_0 = 0xc0000000
PARAMETER C_IPIF_HIGHADDR_0 = 0xdfffffff
PARAMETER C_IPIFBAR_1 = 0xf0000000
PARAMETER C_IPIF_HIGHADDR_1 = 0xf3ffffff
BUS_INTERFACE MPLB = ppc440_0_SPLB0
BUS_INTERFACE SPLB = plb_v46_0
PORT AD = fpga_0_PCI32_BRIDGE_AD_pin
PORT CBE = fpga_0_PCI32_BRIDGE_CBE_pin
PORT PAR = fpga_0_PCI32_BRIDGE_PAR_pin
PORT FRAME_N = fpga_0_PCI32_BRIDGE_FRAME_N_pin
PORT TRDY_N = fpga_0_PCI32_BRIDGE_TRDY_N_pin
PORT IRDY_N = fpga_0_PCI32_BRIDGE_IRDY_N_pin
PORT STOP_N = fpga_0_PCI32_BRIDGE_STOP_N_pin
PORT DEVSEL_N = fpga_0_PCI32_BRIDGE_DEVSEL_N_pin
PORT PERR_N = fpga_0_PCI32_BRIDGE_PERR_N_pin
PORT SERR_N = fpga_0_PCI32_BRIDGE_SERR_N_pin
PORT GNT_N = fpga_0_pci_arbiter_0_PCI_Gnt_n_pin_vslice_0_0_concat
PORT RST_N = net_vcc
PORT PCLK = pci_feedback_s
PORT RCLK = clk_200_0000MHz
PORT REQ_N_toArb = fpga_0_pci_arbiter_0_PCI_Req_n_pin_vslice_0_0_concat
PORT FRAME_I = net_bsbassign0
PORT IRDY_I = net_bsbassign2
PORT IP2INTC_Irpt = PCI32_BRIDGE_IP2INTC_Irpt
END

BEGIN plb_v46
PARAMETER INSTANCE = ppc440_0_SPLB0
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER C_MEM_WIDTH = 16
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END

BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN util_reduced_logic
PARAMETER INSTANCE = ORGate_1
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 2
PARAMETER HW_VER = 1.00.a
PORT Op1 = sys_rst_s & 0b0
PORT Res = fpga_0_ORGate_1_Res_pin
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 125000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 125000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT3_FREQ = 200000000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKOUT4_FREQ = 33333333
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PARAMETER C_CLKOUT4_BUF = TRUE
PARAMETER C_CLKOUT5_FREQ = 62500000
PARAMETER C_CLKOUT5_PHASE = 0
PARAMETER C_CLKOUT5_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT5_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.02.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
PORT CLKOUT1 = clk_125_0000MHzPLL0
PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
PORT CLKOUT3 = clk_200_0000MHz
PORT CLKOUT4 = clk_33_3333MHz
PORT CLKOUT5 = clk_62_5000MHzPLL0_ADJUST
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_cntlr_inst
PARAMETER HW_VER = 2.01.c
BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 3.00.a
BUS_INTERFACE RESETPPC0 = ppc_reset_bus
PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
PORT Ext_Reset_In = sys_rst_s
PORT Dcm_locked = Dcm_all_locked
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Intr = PCI32_BRIDGE_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & xps_timer_0_Interrupt & fpga_0_PCI32_BRIDGE_PCI_INTA_pin & fpga_0_PCI32_BRIDGE_PCI_INTB_pin & fpga_0_PCI32_BRIDGE_PCI_INTC_pin & fpga_0_PCI32_BRIDGE_PCI_INTD_pin & fpga_0_PCI32_BRIDGE_PCI_SBR_INT_pin
PORT Irq = ppc440_0_EICC440EXTIRQ
END

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Accepted Solutions
luisb
Xilinx Employee
Xilinx Employee
7,820 Views
Registered: ‎04-06-2010
Have you tried creating a new project? It's possible the project is corrupt.

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luisb
Xilinx Employee
Xilinx Employee
7,821 Views
Registered: ‎04-06-2010
Have you tried creating a new project? It's possible the project is corrupt.

View solution in original post

samboy786
Visitor
Visitor
5,974 Views
Registered: ‎11-23-2011

I have tried it many a times ... i keep getting the same error-

ERROR:EDK - intc () - Internal error: Number of interrupt inputs on xps_intc_0
(2) is not the same as length of total number of interrupt sources (6). If
any interrupt source is a vector then libgen does not support this use case 
MFS generate ...

ERROR:EDK:3416 - Error(s) while running TCL procedure generate().

 

 

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htsvn
Xilinx Employee
Xilinx Employee
5,965 Views
Registered: ‎08-02-2007

Hi,

 

What is the OS that you are using? How does your MSS look like, i have tried to include MFS and was able to generate BSP for Standalone OS.

 

Thnx

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samboy786
Visitor
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5,960 Views
Registered: ‎11-23-2011

@hem_8030 and luisb

I think i have the answer now... :)
I have changed the workspace and its working well now...
Thanks for all the help
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w8ryan
Visitor
Visitor
5,923 Views
Registered: ‎02-17-2009

Good to know you fixed this... but what do you mean by changed the workspace? BTW - I have the same problem.

WBB

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yinlinlijuan
Adventurer
Adventurer
5,894 Views
Registered: ‎03-14-2012

Hello, I have the same problem,but I do not to solve it; Help!!!:smileysad:

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