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Adventurer
Adventurer
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Registered: ‎11-17-2009

Problem with adding external ports from custom peripheral

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Hi,

 

I am using virtex-5,lx50t device & EDK 11.4. I have created a microblaze processor and have added a custom peripheral to it. Problem occures when I tried to export some ports from custom peripheral (I want to export some ports from custom peripheral  so that I can pass some values to custom peripheral). I followed the procedure for "Modifying the CIP Wizard Template Files" given in chapter 7 of ug683-EDK11.pdf(EDK Concepts, Tools,and Techniques). When I generate netlist 1 error occurs, log of which is attached, when I removed that signal in both vega.vhd & user_logic.vhd and repeat the procedure for "Modifying the CIP Wizard Template Files", then same error is generated for another port.

 

Any help will be highly appreciated

 

Regards,

uzair

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Adventurer
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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I am using ISE as top level, but it generates the error during generating netlist (ie before going to ise project)

 

 

Thanks & Regards,

uzair

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Adventurer
Adventurer
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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Hi again

 

Just to elaborate it further.

Actually i was able to create two external ports using "Modifying the CIP Wizard Template Files" as mentioned above named "Mem_Wr" & "Mem_Rd". Then i modified it and added 7 more signals but i got problem mentioned above. Now just to check, I have opened the last project from backup folder having only two external ports, A strange thing is there. when i add ports or even rename the existing ports, Re-import the design using "Create or Import Peripheral wizard", make that an external port in assembly view, generates netlist, I struck the same problem as above. but when i change back them to "Mem_Wr" & "Mem_Rd" and repeat the process, every thing is fine and netlist is generated successfully.

Its a very strange thing and seems to be a bug of XPS 11.4. I am attaching both of my  XPS projects. (One has two external ports "Mem_Wr" & "Mem_Rd" and in another i have just renamed "Mem_Wr" to "Mem_Wr_Ad" and Re-import it using CIP wizard, every thing ) One generates netlist correctly other does not.

Here I thing it would be worth to mention it that I followed the procedure for "Modifying the CIP Wizard Template Files" given in chapter 7 of ug683-EDK11.pdf(EDK Concepts, Tools,and Techniques)
 
I couldn't  attach the file (seems a problem with website)so uploaded it to rapidshare, here is the link
 

 

Any kind of help will be highly appreciated


Regards,
uzair
 
Message Edited by mm_uzair on 12-16-2009 11:24 PM
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Explorer
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Registered: ‎05-15-2009

Re: Problem with adding external ports from custom peripheral

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I'm not sure if this is what you want, but you can make your custom core ports external by simply changing them in the "Ports" section of System assembly View in EDK. Then route them correctly on the UCF. If you just want to make them available for other cores to connect to it, just do the connections there placing the correct signal names. To add or remove ports after the core wizard you have to add (and route) them to both user logic and top vhd layers of your core.

 

Best,

JM

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Adventurer
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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Hi JM,

How can i make External Ports just by marking them external? how to route them through ucf ? when there is no port there. Off course i want port through which i can communicate to other modules, but i would be happy if you explain your procedure.

I think the only way to get External Port is modify top vhd and userlogic & then modify the re- importing using CIP Wizard as explained in "Modifying the CIP Wizard Template Files" given in chapter 7 of ug683-EDK11.pdf(EDK Concepts, Tools,and Techniques)

 

Regards,

uzair 

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Explorer
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Registered: ‎05-15-2009

Re: Problem with adding external ports from custom peripheral

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Mabe you are messing up the concepts, or i can be missing your point. When you mark a port as External by choosing "Make External" on the ports tab in System Assembly View, its signal will be visible outside the processor architecture for you to use it with outside vhd modules or peripherals. You don't need to make the port external if you just want to connect the signal to other modules (cores) in the processor architecture. External ports are useful if, for instance, you are instantiating your uB architecture in a top level vhd in ISE, or if you want to connect signals in your core to board peripherals.

 

The UCF will route your signals to FPGA pins connected to board peripherals (among many other things such as defining timing constraints), you don't need this otherwise.

 

[EDIT]

And like I said in the other post, and as it is recommended, if you want to add ports to your core after it has been created, you have to change both user logic and top level on your core to include the ports and route them (from user logic to top level which makes them accessible), then reimport the core with the CIP (Create or Import Peripheral) Wizard. This will "refresh" the core and make your new ports available in the Ports view. Remember, this procedure adds signals to your core, it does not make them "External".

 

Best,

JM

Message Edited by jmonteiro-dme on 12-17-2009 03:54 AM
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Adventurer
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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yes exactly i am doing this as you have said

"if you want to add ports to your core after it has been created, you have to change both user logic and top level on your core to include the ports and route them (from user logic to top level which makes them accessible), then reimport the core with the CIP (Create or Import Peripheral) Wizard. This will "refresh" the core and make your new ports available in the Ports view"

 

, then i mark them make external but when i generate netlist it generates the error 

 

"ERROR:NgdBuild:76 - File "../implementation/vega_0_wrapper.ngc" cannot be merged

   into block "vega_0" (TYPE="vega_0_wrapper") because one or more pins on the

   block, including pin "Mem_Wr_Ad<0>", were not found in the file.  Please make

   sure that all pins on the instantiated component match pins in the

   lower-level design block (irrespective of case).  If there are bussed pins on

   this block, make sure that the upper-level and lower-level netlists use the

   same bus-naming convention."

 

How to solve this, have seen projects i have uploaded on rapidshare? 

 

Regards,

uzair 

Message Edited by mm_uzair on 12-17-2009 04:27 AM
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Explorer
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Registered: ‎05-15-2009

Re: Problem with adding external ports from custom peripheral

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It seems you have a problem in the signal name declaration from user logic and in the top level file. Also, make sure you have routed the signal correctly in the top level file. For clarity, use the same name in both user and top level.

 

Best,

JM

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Adventurer
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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No that's not the case, declaration in vega.vhd & user_logic.vhd both are same, you can verify this from the projects which i have uploaded, then you might be able to help me

 

Regards,

uzair 

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Explorer
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Registered: ‎05-15-2009

Re: Problem with adding external ports from custom peripheral

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Yes, you have it correctly instantiated and routed. Are you using ISE as top level or is your project an EDK stand alone? You may have changed the signal names and forgot to change the uBlaze instantiation signal names in the top level.
Message Edited by jmonteiro-dme on 12-17-2009 07:51 AM
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Registered: ‎11-17-2009

Re: Problem with adding external ports from custom peripheral

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I am using ISE as top level, but it generates the error during generating netlist (ie before going to ise project)

 

 

Thanks & Regards,

uzair

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Observer
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Registered: ‎12-18-2009

Re: Problem with adding external ports from custom peripheral

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Hi Uzair,

 

I am also getting somwhat similar problem, it might be a flaw in 11.4,perhaps some xilinx employe can give better answer

 

 

Cheers,

hus

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