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Contributor
Contributor
5,990 Views
Registered: ‎09-17-2008

Problem with creating distributed ram block from core generator and import into XPS

What I want is to create a block of distributed ram using CORE GENERATOR and then importing it into XPS as an IP core.

It might just be me but I can't seem to figure out how to do that. 

When I create the core using CORE GENERATOR I get  some different files:

.ngc .vhd .vho .xco .xrpt .tcl .txt

 

But how to get from these files to actually be able to import and use the distributed ram block in XPS?

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7 Replies
Historian
Historian
5,981 Views
Registered: ‎02-25-2008

Re: Problem with creating distributed ram block from core generator and import into XPS


onklen wrote:

What I want is to create a block of distributed ram using CORE GENERATOR and then importing it into XPS as an IP core.

It might just be me but I can't seem to figure out how to do that. 

When I create the core using CORE GENERATOR I get  some different files:

.ngc .vhd .vho .xco .xrpt .tcl .txt

 

But how to get from these files to actually be able to import and use the distributed ram block in XPS?


Why bother with the Core Generator? Just write ten lines of VHDL that infers the memory and be done with it.

 

-a

----------------------------Yes, I do this for a living.
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5,965 Views
Registered: ‎08-21-2008

Re: Problem with creating distributed ram block from core generator and import into XPS

Hello.

You can import XPS in ISE and ISE in XPS also.

Importing XPS in ISE is easy and efficient.

Importing ISE in XPS is tedious and also not recommended by Xilinx.

So its better you create an IP in ISE using coregen and import XPS in ISE also and do the proceedings in ISE.

Best of luck.
--
Unlimited in my Limits.
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Contributor
Contributor
5,929 Views
Registered: ‎09-17-2008

Re: Problem with creating distributed ram block from core generator and import into XPS

So I created a new ISE project and imported my XPS project which worked fine. I then used Core Generator to create some distributed ram. When creating this distributed ram I get an .xco file in my project. But I'm still having a hard time finding out how to add this distributed ram so I can use it in EDK and eventually in SDK.

Any good user guides or can someone please explain how to do that? 

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Historian
Historian
5,925 Views
Registered: ‎02-25-2008

Re: Problem with creating distributed ram block from core generator and import into XPS


onklen wrote:

So I created a new ISE project and imported my XPS project which worked fine. I then used Core Generator to create some distributed ram. When creating this distributed ram I get an .xco file in my project. But I'm still having a hard time finding out how to add this distributed ram so I can use it in EDK and eventually in SDK.

Any good user guides or can someone please explain how to do that? 


DON'T USE THE CORE GENERATOR.

 

Write the very simple VHDL that infers the memory.

 

-a

----------------------------Yes, I do this for a living.
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5,915 Views
Registered: ‎08-21-2008

Re: Problem with creating distributed ram block from core generator and import into XPS

Hello.

What you can do is whatever signals you have in your ram module(Coregen) you can trigger them using the signals generated in EDK. Signals you can take like 1 bit GPIO LEDs and Dip Switches to create enable signals that will be mapped to enable signals of your distributed ram in ISE.

if your data width of RAM is 8 bit then you can take again 8 bit GPIO LEDs and Dip Switches to take data in and out of EDK and map to data signal of your RAM in ISE.

Remember enable signals will be a pulse so in EDK for one clock cycle you have to push 1 and then in the next cycle you have to push 0 and then data can be read at the address you want. 

Best of luck.
--
Unlimited in my Limits.
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Contributor
Contributor
5,898 Views
Registered: ‎09-17-2008

Re: Problem with creating distributed ram block from core generator and import into XPS

I think I get the idea about how to connect e.g. a GPIO from XPS to the ram module. My main problem is that so far I have only used EDK and SDK and I have no experience in using ISE.

 

As I understand I import my XPS project as a top module and then create (using Coregen) a sub-module (distributed ram). My question is then how do I tell my top-module to include the sub-module and how to connect the ports from EDK to the ports in my sub-module?

 

If I look at the "View HDL Instatiation Template"  for my XPS module I can see all the extern ports. I'm guessing some of them should be connected to the distributed ram module. But how to I connect these two? Is that something I should do within the HDL code of the distributed ram modul?

 

 

 

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5,894 Views
Registered: ‎08-21-2008

Re: Problem with creating distributed ram block from core generator and import into XPS

Hello.

Your ise will be the top module. In that distributed ram and XPS will be the components (sub modules).

What you do is that you do NEW SOURCE in ISE and select embedded and then you make your system in XPS. After completing your system(HW+SW) in XPS you go for generate netlist only. Do not generate bitstream over there in XPS. Please note you have to give your final UCF in ise only.

Then you port map in ISE the XPS as it will be available to you in the form of component. You highlite XPS in ISE in the sources window and in the processes tab you will see "View hardware instantiation template". Go for this option and Component will be generated by the tool itself.

Similarly coregen will also produce a component.

Then you can play in ISE with both the components.

Main entity will consist of all the ports interfacing to the external world of FPGA. 

 

Best of luck.
--
Unlimited in my Limits.
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