We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎02-09-2009

Problem with setting up a PLB P2P connection between MAster PLB device and memoty

Hey everyone!


Here is the story:


I'm using EDK 9.2 and the Virtex4-FX FPGA.


I designed a PLB v4.6 master device, that also supports P2P (Peer-2-Peer) connection. I would like to connect it with a MPMC via the P2P connection.


To the plb bus that connects my peripheral and the mpmc, nothing else is connected (no cpu, no other peripheral)


When I don't set any P2P parameters (neither in the bus instance, nor in the mpmc, in the designed peripheral) everything works fine.


However, after enabling P2P parameter in the bus instance connecting my periph. and the mpmc, libgen generates error:


"C_P2P parameter value  is set to 1 in MHS, when the P2P mode is not supported by the master/slave on the bus..."


There is also information that "...tool is overriding PARAMETER C_DPLB0_P2P value to 0"


How come, parameters of the PPC405 affect (leads to overriding) parameters of some bus not connected to the CPU?


It seems that Platgen always counts the CPU as a bus master, no matter whether it is connected to the bus or not.


Is there any way to overcome this bug or I'm bound to "shared" PLB connection with all the arbitration logic and related latency, though only 2 devices, the master and the slave are present on the bus? 


Thx in adv!



0 Kudos