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Newbie
Newbie
1,835 Views
Registered: ‎05-17-2014

Problems interfacing with AXI bus

Hi, not sure if this is the right place to post this but I'm having issues interfacing a custom peripheral with the  AXI bus.

I'm using Xilinx Studio, I've made just a simple register module so I want to write to it and read from it via the AXI4Lite bus.

 

This is the architecture of the user_logic:

 

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

COMPONENT register_topnodule
    PORT(
        clk : IN std_logic;
        wen : IN std_logic;
        rst : IN std_logic;
        read_ce : IN std_logic;
        write_ce : IN std_logic;
        dataIN : IN std_logic_vector(7 downto 0);          
        read_ack : OUT std_logic;
        write_ack : OUT std_logic;
        dataOUT : OUT std_logic_vector(7 downto 0)
        );
    END COMPONENT;

SIGNAL read_ce_logic : STD_LOGIC;
SIGNAL write_ce_logic : STD_LOGIC;

begin

read_ce_logic <= Bus2IP_RdCE(C_NUM_REG-1);
write_ce_logic <= Bus2IP_WrCE(C_NUM_REG-1);
 
--Static error value
    IP2Bus_Error <= '0';


    Inst_register_topnodule: register_topnodule PORT MAP(
        clk => Bus2IP_Clk,
        wen => Bus2IP_Data(8),
        rst => Bus2IP_Data(9),
        dataIN =>  Bus2IP_Data(7 downto 0),
        read_ce => read_ce_logic,
        write_ce => write_ce_logic,
        read_ack => IP2Bus_RdAck,
        write_ack => IP2Bus_WrAck,
        dataOUT => IP2Bus_Data(7 downto 0)
    );

 

Note: inside the register module I made if read_ce or write_ce (aka the requests) are at logic '1' then the same acknowledge is sent back, otherwise they stay at '0'

 

 

If the question is a bit vague or unclear, feel free to ask for additional information, I'm just starting out using this interface for a university assignment and I'm well stuck with it.

 


Thanks in advance

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Highlighted
Xilinx Employee
Xilinx Employee
1,812 Views
Registered: ‎08-02-2007

Re: Problems interfacing with AXI bus

Hi,

 

I am not sure what is the issue here. However refer to the link which goes through the procedure of accessing the register

 

Do explain what problem you are seeing.

 

--Hem

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