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Participant lee_xiao
Participant
6,857 Views
Registered: ‎02-25-2014

Problems on using axi_ethernet

Hi,

 

I am trying to transferring and receiving data in FPGA by using axi_ethernet IP. I have built a simple system (please see the attached). I have not got any problem during synthesing, implementation and exporting the project to the SDK. However, when I was generating a new application project using "Hello world", It seems the SDK failed to generate the BSP. Please see the error message in the attached file. The version of Vivado and SDK of which I am using is 2014.2 and I am using a zc706 evaluation board.

 

I am very grateful if you can give me some help.

 

 

Regards.

 

 

Lee Xiao

sdk_error.jpg
ethernet_bd.jpg
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9 Replies
Xilinx Employee
Xilinx Employee
6,847 Views
Registered: ‎08-02-2007

Re: Problems on using axi_ethernet

Hi,

 

Looking at the error it looks like BSP is looking an interrupt controller connected to axi_ethernet.

 

--Hem

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Participant lee_xiao
Participant
6,833 Views
Registered: ‎02-25-2014

Re: Problems on using axi_ethernet

Thank you for your help.

 

I add an interrupt controller (Please see the attached). Re-synthesised and implemented the project and exported to the SDK. Then I tried to create a "hello world" project with SDK. The SDK still failed to generate the BSP and it seems this time the SDK was complaining about AXI4-Stream FIFO IP (please see the attached error message).

 

However, for the same project (block diagram), when I was using Vivado and SDK 2013.4 to synthesis, implement and export

the project to the SDK (2013.4), I did not have any problem creating a "hello world" project with the SDK. However, when I was testing the xaxiethernet_example_intr_fifo(axirthernet_v3_02_a). It seems the MgtRdy bit of the Interrupt Status Register of the AXI Ethernet IP

does not go to '1'. This means the serial transceiver is not ready to use.

 

I don't know what has caused this problem We are very grateful if you can help us solve this problem.

 

Regards.

 

 

Lee

ethernet_bd.jpg
sdk_error.jpg
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Scholar sampatd
Scholar
6,806 Views
Registered: ‎09-05-2011

Re: Problems on using axi_ethernet

I have seen a similar issue, but with axi ethernetlite. Check the AR below:
http://www.xilinx.com/support/answers/61185.html
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6,298 Views
Registered: ‎02-07-2008

Re: Problems on using axi_ethernet

Hi,

 

Just want to bump this post because I'm having exactly the same problem. I'm using Vivado 2014.2, my design is for the ZedBoard, I have 3 AXI Ethernet blocks all configured with DMAs. The design passes through to bitstream and exports to SDK without problems. However, when I try to generate a "hello world" application from the templates, I get the following error in the log shown below.

 

If you would like to reproduce the error, the code is shared here on Github:

 

https://github.com/fpgadeveloper/zedboard-qgige

 

Here is the error log:

 

14:15:22 INFO    : Processing command line option -hwspec E:/Github/fpgadeveloper/zedboard-qgige/Vivado/zedboard_qgige/zedboard_qgige.sdk/design_1_wrapper.hdf.
14:15:22 INFO    : Checking for hwspec changes in the project design_1_wrapper_hw_platform_0.
14:15:45 ERROR    :  [Common 17-161] Invalid option value '' specified for 'object'.
 [Hsm 55-1545] Problem running tcl command ::sw_axiethernet_v4_1::generate : ERROR: [Common 17-161] Invalid option value '' specified for 'object'.
    while executing
"get_property IP_TYPE $pname_type"
    ("foreach" body line 4)
    invoked from within
"foreach intr_sink $intc_port {
        set pname_type [get_connected_interrupt_controller $target_periph $intr_sink]
                if {$pname_type != "chi..."
    ("foreach" body line 9)
    invoked from within
"foreach intr_port $interrupt_port {
        set interrupt_signal_name [get_property NAME $intr_port]
        set intc_port [get_pins -of_objects $targ..."
    (procedure "xdefine_dma_interrupts" line 20)
    invoked from within
"xdefine_dma_interrupts $file_handle $target_periph $device_id $canonical_tag $dmarx_signal $dmatx_signal"
    ("foreach" body line 84)
    invoked from within
"foreach periph $periphs {
        set p2p_periphs [list]
        set periph_name [string toupper [get_property NAME $periph]]
    # Get all point2point b..."
    (procedure "xdefine_axi_target_params" line 17)
    invoked from within
"xdefine_axi_target_params $periphs $file_handle"
    (procedure "xdefine_axiethernet_include_file" line 46)
    invoked from within
"xdefine_axiethernet_include_file $drv_handle "xparameters.h" "XAxiEthernet""
    (procedure "::sw_axiethernet_v4_1::generate" line 3)
    invoked from within
"::sw_axiethernet_v4_1::generate axi_ethernet_0_eth_buf"
 [Hsm 55-1442] Error(s) while running TCL procedure generate()
14:15:45 ERROR    : Error generating bsp sources: Failed to generate BSP.

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6,259 Views
Registered: ‎02-07-2008

Re: Problems on using axi_ethernet

I'm replying to answer my own message just for anyone with the same problem.

 

I eventually solved my problem by hooking up the AXI Ethernet and DMA interrupts to the Zynq PS.

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Contributor
Contributor
6,172 Views
Registered: ‎07-10-2013

Re: Problems on using axi_ethernet

Lee,

 

Did you solve your problem with MGTRDY bit not going high? With Vivado 2014.3 and VC-707 board we are experiencing exactly the same behaviour. In V2013.4 everything was OK, and V2014.2 gave some strange errors while building the project that were told to be corrected in 2014.3, so we abandoned it.

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Contributor
Contributor
6,091 Views
Registered: ‎07-10-2013

Re: Problems on using axi_ethernet

Update:

 

1. No matter whether we use KC-705 or VC-707 board, the result of the design in V2014.3 is the same: MgtRdy bit not going high.

2. Increasing the loop count waiting for MgtRdy going high also doesn't change the thing.

3. In V2014.3 we use axi_ethernet v6.2 (doesn't work), in V2013.4 we use axi_ethernet v6.0 (seems to work OK).

The part of the block diagram is below:

 

axi_eth.jpg

 

Have we forgot about something?

Is mac_irq signal to be served by interrupt controller obligatory?

Any help from Xilinx?

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Highlighted
Visitor nemmo0
Visitor
4,142 Views
Registered: ‎08-09-2014

Re: Problems on using axi_ethernet

I have had a similar problem. In my case the interrupt of AXI_Ethernet_Subsytem was tied to the Interrup Controller however the interrupt output of the Ethernet FIFO was floating. When I also connected that to the Interrupt Controller the BSP was successfully generated.

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Observer igorauad
Observer
3,484 Views
Registered: ‎11-16-2015

Re: Problems on using axi_ethernet

Hi,

 

I know it has been quite a long time since you posted. Do you remember whether this issue has a solution? I am experiencing the same here.

 

Thanks in advance.

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