11-20-2009 07:47 AM - edited 11-20-2009 07:48 AM
I am aware of the fact, that this is a newbie question. Anyway, I am having problems with adding the Xilinx IIC IP core to my Microblaze project. Here's what I do:
I am adding the IP core from the catalog. The IP appears on the list as xps_iic_0. No problems here. Next, I select 'Bus interfaces' in the 'System assembly' window and connect the SPLB of the IP core to the mb_plb bus. Looks OK, the connection is made (the dot symbol appears in the left part of the window). The IP is now connected, but no bus address is assigned to it. I move to the 'Addresses' tab in the 'System assembly' window and click on 'Generate addresses'. The address assigned to the IP core looks OK, there are no conflicts with other parts of the system. The corresponding part of the MHS file looks like this:
PARAMETER INSTANCE = xps_iic_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81600000
PARAMETER C_HIGHADDR = 0x8160ffff
BUS_INTERFACE SPLB = mb_plb
Now, I move to the 'Ports' tab in the 'System assembly' window and make the 'Scl' and 'Sda' ports external. The following ports appear in the MHS file:
PORT xps_iic_0_Sda = xps_iic_0_Sda, DIR = IO
PORT xps_iic_0_Scl = xps_iic_0_Scl, DIR = IO
I modify the UCF file for the project by adding:
Net xps_iic_0_Sda LOC=F8 | IOSTANDARD = LVCMOS33 | PULLUP;
Net xps_iic_0_Scl LOC=E8 | IOSTANDARD = LVCMOS33 | PULLUP;
When I try to create a bitstream, I get the following message:
WARNING:EDK:2137 - Peripheral xps_iic_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters.
Also, the 'Slaves of mb_plb' part of the block diagram shows, that the IIC IP core is not connected (no dot symbolizing 'slave or target').
I am obviously doing something wrong, but have no idea what. I'd really, really appreciate any help from the forum gurus. Thanks in advance.
My EDK version is 11.3, running on Ubuntu 9.10 linux.
11-20-2009 07:50 AM
Just proceed with generating the address.
Try to access the core. I dont think it should be a problem.
11-21-2009 03:22 AM - edited 11-21-2009 03:26 AM
I guess we are facing a very similar problem, I also try to add an IP to the whole system as a PLB slave, but the address can not be mapped to the processor's addressing space. It's weird.
I don't have answer for this problem. But if I ignore it, I can not access that IP using the processor MicroBlaze or XMD MRD/MWR command.
02-10-2010 05:35 AM
I have added two standard IP cores from the catalog including an IIC and GPIO to the "Tutorial Sandbox" for the SP506 Spartan 6 Embedded Board. These are to support an FMC daughter card that I have designed and built and want to integrate and test.
Everything seems to build OK but when I go to actually run it in the SP506 I do not see either the added IIC or GPIO when I access the memory locations they are mapped at either through my application or XMD.
I am running EDK 11.4 but have seen this problem in the past with possibly vers 8.2 and 10.1. In those cases if I had the XPS(EDK) tool generate a Test App for them the added IP would work fine but otherwise they were not accessible to the CPU even though they are shown in the address space for EDK.
I tried turnig off the MMU (thinking it was a virtual mapping issue) rebuilt and the problem is the same.
I Check the MHS and MSS file and compared my added GPIO with the LED4 that is already there and cannot see the difference. I have checked the build logs and did not see any warnings related to this.I have also tried a generate addresses but this changed the DDR3 and BRAM locations that I had to correct and then had to fix the Microblaze I/D Cache ranges. I am now building this one but don't expect a fix.
Somehow it seems that the microblaze does not have these added IP in its memory map at the locations they should be at.
02-19-2010 02:51 AM
Clean your hardware and software from XPS.
Click the generate addresses button and make sure you have an address assigned to the core, if not check that you have the core connected to a PLB that is accessable from the CPU. If you have a memory controller and a PLB port on the controller for DMA purposes and your core is connected to that PLB then typically you won't have an accessable address.
I struggled with this one for a while too.
In SDK, clean your projectes and rebuild to ensure anything stale does not affect you.