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kkoorndyk
Contributor
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Registered: ‎02-12-2009

Problems with hard emac in Virtex 5

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I've run through the tutorial to add a microblaze and temac without a problem.

 http://www.xilinx.com/products/boards/ml505/ml505_10.1_3/docs/ml505_std_ip_pcores_sgmii_addition.pdf

 

Now I'm trying to spin my own design from scratch using BSB.   I want a SGMII, so when I set the *GMII* signals to No Connection (slide 25) and then set the MGT signals to External Connection (slide 26) the UCF keeps the constraints on the *GMII* signals but the HDL doesn't.  So it errors out during NGDBuild when it reaches those constraints.

 

If I comment out those constraints, it makes to MAP but dies with the following errors:

 

ERROR:PhysDesignRules:1742 - Unsupported GTX_DUAL programming for comp
   Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0
   _rocketio_wrapper_gtx_i/gtx_dual_i. The OOBDETECT_THRESHOLD_0 general config data setting 001 is not supported. The
   allowed values for OOBDETECT_THRESHOLD_0 are 110 and 111. Please re-generate this component in the latest version of
   Coregen to fix this error. If the error persists, please open a case with Xilinx Technical Support to report this
   problem.
ERROR:PhysDesignRules:1742 - Unsupported GTX_DUAL programming for comp
   Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0
   _rocketio_wrapper_gtx_i/gtx_dual_i. The OOBDETECT_THRESHOLD_1 general config data setting 001 is not supported. The
   allowed values for OOBDETECT_THRESHOLD_1 are 110 and 111. Please re-generate this component in the latest version of
   Coregen to fix this error. If the error persists, please open a case with Xilinx Technical Support to report this
   problem.
ERROR:Pack:1642 - Errors in physical DRC.

 

 

I tried applying the patch found here, but it didn't work.

 

 

Anybody else have any trouble with this?  Any other solutions?

DornerWorks
https://goo.gl/LNexn5



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kkoorndyk
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Registered: ‎02-12-2009

So I figured it out with some help from a Xilinx rep.   I had to click Hardware -> Clean Hardware and then rebuild and everything is happy.

 

 

DornerWorks
https://goo.gl/LNexn5



Xilinx Alliance Program - Premier Tier

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jeffrey.johnson
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Registered: ‎02-07-2008
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kkoorndyk
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Registered: ‎02-12-2009

So I figured it out with some help from a Xilinx rep.   I had to click Hardware -> Clean Hardware and then rebuild and everything is happy.

 

 

DornerWorks
https://goo.gl/LNexn5



Xilinx Alliance Program - Premier Tier

View solution in original post

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