Hi, I'm trying to profile a PowerPC application that is using an OPB Timer interrupt.
I choosed PIT as my profiling timer.
The problem is that, there is some kind of conflict between the two interrupt sources.
At the beginning the program runs fine, but when it arrives at the line that enables the
OPB Timer interrupt, the application just freeze and doesn't goes any further.
When I erase the line that enable the OPB Timer interrupt, the program runs until the end, but of course,
the functionality of the software is not ok because It needs an OPB Timer Interrupt to deliver data correctly.
At Xilinx Site, I found the answer AR #31559 http://www.xilinx.com/support/answers/31559.htm,
where it says that there is a problem when two timers are present, and that this problem
is fixed in SP3 for EDK 10.1.
Im using EDK 9.1 SP2, so, is it a known problem on the version I'm using? If so, there is a software patch to fix the problem?
If not is the case, there is a something wrong with my code? I copy the OPB Timer configuration code:
XIntc_mMasterEnable(XPAR_OPB_INTC_0_BASEADDR); XIntc_SetIntrSvcOption(XPAR_OPB_INTC_0_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
XTmrCtr_mSetLoadReg(XPAR_OPB_TIMER_1_BASEADDR, 0, 10000);
XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK| XTC_CSR_DOWN_COUNT_MASK);