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jimg@crypto4a.com
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Registered: ‎05-11-2018

QSPI in FSBL loading {PL bitfile + application ELFs} from eMMC on Zynq US+

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Hello,

I've seen queries describing how to do this on the Zynq 7000 platform, but not Zynq US+ so I thought I'd ask what I'm sure are very simple questions to try and sort out how to do this on the MPSoC platform:

  1. How do I set things up to load my FSBL into the QSPI and have it then read in the PL bitfile and APU/RPU applications from the eMMC? Let's not worry about secure boot or any other complications at this point. I just want to be able to write a FSBL.bin file to QSPI, and a BOOT.bin file containing all of the PL/APU/RPU images to the eMMC in such a way that the FSBL reaches out to the eMMC to load BOOT.bin. I know how to use bootgen and the like, but it's not clear how to tell the FSBL to go fetch the remaining partitions from eMMC without having to customize the FSBL code.
  2. Do I need to customize the FSBL code to make this happen? If so, then what explicitly do I need to modify (e.g., do I explicitly set the PrimaryBootDevice to point to eMMC)?
  3. Are their build flags/options or bootgen hooks for generating the necessary bin files that will make this all work w/o having to tweak the FSBL? If so, what are the specific steps/options I need to apply/modify?
  4. Is this documented somewhere in the mountains of UG/XAPP/WP documents on Xilinx's website so that I don't have to keep clogging up the community forums with these sorts of questions?

  Thanks in advance for any insights you may all have to help me demystify this process!

  Take care.

Jim

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jimg@crypto4a.com
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Registered: ‎05-11-2018

Managed to figure things out with a bit of digging into the confluence wiki. Here's a detailed explanation in the hopes of saving others some time in the future:

  • Create your FSBL ELF file, PL bit image, and APU/RPU ELF file(s) using the standard Xilinx toolchains.  I'm doing this on the "old" SDK tool flows, I have no idea how using the new Vitis tools changes things.
  • Create two BIF files (call them "primary.bif" and "secondary.bif" for reference. The first (i.e., primary.bif) only includes information related to the FSBL that will be loaded into the primary boot device (QSPI32 in my case), along with the boot_device directive that points to the secondary boot device (eMMC in my case) where it will find the PL/APU/RPU images. The second (i.e., secondary.bif) looks like your standard bif file where we include ALL of the images (including the FSBL). Do NOT forget to include the FSBL image in this file or it won't work.

 

// primary.bif - using 32-bit FSBL image contained in fsbl.bif and our secondary device where we store 
// the PL/APU/RPU images will be the emmc (just change that to whatever your application requires)
the_ROM_image:
{
    [fsbl_config] a53_x32
    [bootloader] fsbl.elf
    [boot_device] mmc
}
// secondary.bif - include all PL/APU/RPU images here that will be loaded from the secondary device
// (note that you MUST include fsbl.elf info or it will NOT work)
the_ROM_image:
{
	[fsbl_config] a53_x32
	[bootloader] fsbl.elf
	[destination_device = pl] top_level.bit
	[destination_cpu = a53-0] core0.elf
	[destination_cpu = a53-1] core1.elf
	[destination_cpu = a53-2] core2.elf
	[destination_cpu = a53-3] core3.elf
}

 

  • Generate a bin file from each of the above bif files. You can name the primary bin file anything you'd like as we're going to be using Xilinx SDK tools to write it to QSPI, but the second image MUST be named BOOT.bin since we're going to be putting it onto the eMMC.

 

bootgen -image primary.bif -arch zynqmp -w on -o ./BOOT_primary.bin
bootgen -image secondary.bif -arch zynqmp -w on -o ./BOOT.bin

 

  • Write BOOT_primary.bin to the QSPI using whatever tooling you have (e.g., Xilinx SDK's Write Flash tool with qspi_single as the target).
  • Write BOOT.bin to eMMC using whatever tooling you have (e.g., Xilinx SDK's Write Flash tool with emmc as the target).
  • Configure the boot mode to be QSPI and then reboot the system. You should be good to go!

A bit counter intuitive (e.g., having to include the FSBL image in the secondary boot device image despite it having already been loaded from the primary boot device), but not too difficult in the grand scheme of things!

Take care.

  Jim

 

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jimg@crypto4a.com
Adventurer
Adventurer
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Registered: ‎05-11-2018

Managed to figure things out with a bit of digging into the confluence wiki. Here's a detailed explanation in the hopes of saving others some time in the future:

  • Create your FSBL ELF file, PL bit image, and APU/RPU ELF file(s) using the standard Xilinx toolchains.  I'm doing this on the "old" SDK tool flows, I have no idea how using the new Vitis tools changes things.
  • Create two BIF files (call them "primary.bif" and "secondary.bif" for reference. The first (i.e., primary.bif) only includes information related to the FSBL that will be loaded into the primary boot device (QSPI32 in my case), along with the boot_device directive that points to the secondary boot device (eMMC in my case) where it will find the PL/APU/RPU images. The second (i.e., secondary.bif) looks like your standard bif file where we include ALL of the images (including the FSBL). Do NOT forget to include the FSBL image in this file or it won't work.

 

// primary.bif - using 32-bit FSBL image contained in fsbl.bif and our secondary device where we store 
// the PL/APU/RPU images will be the emmc (just change that to whatever your application requires)
the_ROM_image:
{
    [fsbl_config] a53_x32
    [bootloader] fsbl.elf
    [boot_device] mmc
}
// secondary.bif - include all PL/APU/RPU images here that will be loaded from the secondary device
// (note that you MUST include fsbl.elf info or it will NOT work)
the_ROM_image:
{
	[fsbl_config] a53_x32
	[bootloader] fsbl.elf
	[destination_device = pl] top_level.bit
	[destination_cpu = a53-0] core0.elf
	[destination_cpu = a53-1] core1.elf
	[destination_cpu = a53-2] core2.elf
	[destination_cpu = a53-3] core3.elf
}

 

  • Generate a bin file from each of the above bif files. You can name the primary bin file anything you'd like as we're going to be using Xilinx SDK tools to write it to QSPI, but the second image MUST be named BOOT.bin since we're going to be putting it onto the eMMC.

 

bootgen -image primary.bif -arch zynqmp -w on -o ./BOOT_primary.bin
bootgen -image secondary.bif -arch zynqmp -w on -o ./BOOT.bin

 

  • Write BOOT_primary.bin to the QSPI using whatever tooling you have (e.g., Xilinx SDK's Write Flash tool with qspi_single as the target).
  • Write BOOT.bin to eMMC using whatever tooling you have (e.g., Xilinx SDK's Write Flash tool with emmc as the target).
  • Configure the boot mode to be QSPI and then reboot the system. You should be good to go!

A bit counter intuitive (e.g., having to include the FSBL image in the secondary boot device image despite it having already been loaded from the primary boot device), but not too difficult in the grand scheme of things!

Take care.

  Jim

 

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jimg@crypto4a.com
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Registered: ‎05-11-2018

Sorry, just a note that I meant to say Xilinx SDK's "Program Flash" tool and not "Write Flash".  It always drives me crazy when posts make little typos like this which leads to doubt in the minds of people who are uncertain. Sorry for the mistake!

Take care.

  Jim

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Bhargava
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693 Views
Registered: ‎10-14-2020

Hi,

We are trying the same fsbl into qspi and secondary boot as  emmc as you mentioned above

primary bif which is flashed into qspi is as follows:

the_ROM_image:
{
[bootloader, destination_cpu=a53-0] zynqmp_fsbl.elf
[boot_device] mmc
}

secondary bif flashed into emmc which is as follows:

the_ROM_image:
{
[bootloader, destination_cpu=a53-0] zynqmp_fsbl.elf
[destination_device = pl] zusys_wrapper.bit
[destination_cpu=pmu] pmufw.elf
[destination_cpu=a53-0, exception_level=el-3, trustzone] bl31.elf
[destination_cpu=a53-0, exception_level=el-2] u-boot.elf
[destination_cpu=a53-0, partition_owner=uboot] image.ub

}

we created BOOT.BIN using below command :

bootgen -image secondary.bif -arch zynqmp -o BOOT.BIN -w

its booting till uboot but unable to find kernel.

Should we mention any offset or any change in environment ?

How to get image.ub or point to kernel which is packed inside BOOT.BIN?

We dont have option of booting from SD card and ethernet.

Uboot environment file is attached for reference.

log is as follows:

U-Boot 2019.01 (Nov 02 2020 - 05:25:52 +0000)

Board: Xilinx ZynqMP
DRAM: 4 GiB
EL Level: EL2
Chip ID: zu4ev
MMC: mmc@ff160000: 0
Loading Environment from SPI Flash... SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
OK
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Board: Xilinx ZynqMP
Net: ZYNQ GEM: ff0b0000, phyaddr ffffffff, interface sgmii
eth0: ethernet@ff0b0000
Hit any key to stop autoboot: 0
Device: mmc@ff160000
Manufacturer ID: 15
OEM: 100
Name: 8GUF4
Bus Speed: 52000000
Mode : MMC High Speed (52MHz)
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: 7.3 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 7.3 GiB WRREL
Boot Capacity: 31.9 MiB ENH
RPMB Capacity: 4 MiB ENH
** Unable to read file image.ub **

 

 

Regards,

Bhargava

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jimg@crypto4a.com
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Registered: ‎05-11-2018

Hello Bhargava,

  I'm guessing your secondary image is a full up Linux (or Petalinux) image, correct?  If so, then you probably have to work some magic on creating the binaries to make it compatible with the Petalinux boot flow.

  This isn't something I'm familiar with though as we're a bare metal shop. I did a quick poke around the forums and found the following link which may (or may not!) be of assistance in this case, though looking at your BIF files they look very similar to what's described in the link so perhaps you've already tried these "tricks":

https://forums.xilinx.com/t5/Embedded-Linux/How-to-create-the-binary-file-with-FPGA-bitstream-fsbl-and-Linux/td-p/795480

  Good luck, I'm sorry I don't have more to offer.

Jim

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Bhargava
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Registered: ‎10-14-2020
Thanks for the reply Jim
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