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Adventurer
Adventurer
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Registered: ‎10-16-2018

Question about vivado2017.4 version

    In the vivado2017.4 version, the PS card is started by the SD card to generate a 100Mhz clock through the fclk0 output. The PL end uses the instantiated ZYNQ core and uses fclk0 as the clock input signal of the top-level module to implement certain functions and generate a bit file through comprehensive implementation.

    In the vivado2017.4 version, the PS card is started by the SD card to generate a 100Mhz clock through the fclk0 output. The PL end uses the instantiated ZYNQ core and uses fclk0 as the clock input signal of the top-level module to implement certain functions and generate a bit file through comprehensive implementation.

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Adventurer
Adventurer
567 Views
Registered: ‎10-16-2018

    Using the SD card to start the PS side to generate 100Mhz fclk0, and then download the bit file through vivado2017.4, the target function cannot be achieved. Using the SD card to start the PS end to generate 100Mhz fclk0, and then download the bit file through vivado2017.2, you can successfully achieve the target function, where is the problem? Is the bug of vivado2017.4 version? Is there any way to solve it?

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