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Registered: ‎09-23-2020

Reprogramming PL using bitstream not working on ZCU106 board when using the XilFPGA library

I am trying to reprogram the PL on a ZCU106 board using a bitstream.  I am doing this by using the XilFPGA library.  Currently, I have the PMU polling for when the MIO 26 pin toggles from low to high.  The PMU then calls the PmReleaseNode on the PL node in order to release it from the APU and power off the PLD.  After the PLD is off, I then run the xfpg_load_bitstream_example.c code (see below) in order to reprogram the bitstream.  The address for the bitstream to be loaded from is the same as the one the FSBL loads the bitstream into.  Typically this is meant to be a temporary address but I have changed it and then configured my linux kernel to treat that address as a reserved portion of memory so that it is not overwritten.  When doing this the PL is rarely reprogrammed correctly.

Is there any reason that would cause the PL to only be programmed correctly sometimes?

When looking at the Power Advantage Tool (see below), I can see that after the PL is reprogrammed the power draw is less than it initially was.  Does anyone have any suggestions as to why this happens?

Reprogram_PL_bitstream.PNG

 

/******************************************************************************
* Copyright (c) 2016 - 2020 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

/*****************************************************************************/
/**
 *
 * @file xfpga_load_bitstream_example.c
 *
 * This file contains the example using Xilfpga library to transfer the user
 * provided Bitstream into zynqmp pl region.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who     Date     Changes
 * ----- ------  -------- ------------------------------------------------------
 * 1.0   Nava    08/06/16  First release
 * 4.0   Nava	21/02/18  Updated the example relevant to src code changes.
 * 4.2   Nava    30/05/18  Refactor the xilfpga library to support
 *                         different PL programming Interfaces.
 * 4.2	 adk	 23/08/18  Added bitstream size define.
 * 5.0   Nava	 06/02/19  Updated the example to sync with 5.0 version API's
 * 5.0	 Nava 	 16/03/19  Typical bitstram size of zcu102 board is 26MB.So
 *			   updated the bitstream size macro value for the same.
 * 5.2   Nava	 14/02/20  Removed unwanted header file inclusion.
 * </pre>
 *
 ******************************************************************************/

#include "xilfpga.h"

/**************************** Type Definitions *******************************/
/* Xilfpga library supports vivado generated Bitstream(*.bit, *.bin) and bootgen
 * generated Bitstream(*.bin), Passing below definition is mandatory for vivado
 * generated Bitstream, For bootgen generated Bitstreams Xilfpga will take
 * Bitstream size from Bitstream Header.
 *
 * Below definition is for typical bitstream size of zcu102 board
 * User should replace the below definition value with the actual bitstream size.
 *
 * @note: This example supports only Zynq UltraScale+ MPSoC platform.
 */
#define BITSTREAM_SIZE	0x1A00000
/*****************************************************************************/
int main(void)
{
	u64 addr = XFPGA_BASE_ADDRESS;
	XFpga XFpgaInstance = {0U};
	s32 Status;

	xil_printf("Loading Bitstream for DDR location :0x%x\n\r",
				XFPGA_BASE_ADDRESS);
	xil_printf("Trying to configure the PL ......\n\r");

	Status = XFpga_Initialize(&XFpgaInstance);
	if (Status != XST_SUCCESS) {
		goto done;
	}

	Status = XFpga_PL_BitStream_Load(&XFpgaInstance, addr,
					 BITSTREAM_SIZE, XFPGA_FULLBIT_EN);

 done:
	if (Status == XFPGA_SUCCESS)
		xil_printf("PL Configuration done successfully");
	else
		xil_printf("PL configuration failed\n\r");

	return 0;
}

 

 https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilfpga/examples/xfpga_load_bitstream_example.c

 

Reprogram_PL_bitstream.PNG
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