cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jguenth1
Newbie
Newbie
737 Views
Registered: ‎07-02-2020

Reset BSP Sources Error with AXI UartLite Interrupts

I've added two AXI uartlite blocks to my design in Vivado 2019.2 but when trying to reset BSP sources in Vitis to update xparameters.h, I get this error:

Error occurred while generating bsp sources for the domain 'standalone_domain'.
Failed to generate the bsp sources for domain.standalone_domain

Details: expected integer but got ""

ERROR: [Hsi 55-1545] Problem running tcl command ::sw_scugic_v4_1::generate : expected integer but got ""
    while executing
"format "#define XPAR_FABRIC_%s_%s_INTR %d$uSuffix"  [string toupper $ip_name] [string toupper $port_name] $port_intr_id"
    ("foreach" body line 115)
    invoked from within
"foreach periph $periphs {

        # get the gic mode information
        set scugic_mode [common::get_property CONFIG.C_IRQ_F2P_MODE $periph]

      ..."
    (procedure "xdefine_gic_params" line 33)
    invoked from within
"xdefine_gic_params $drv_handle"
    (procedure "::sw_scugic_v4_1::generate" line 10)
    invoked from within
"::sw_scugic_v4_1::generate ps7_scugic_0"

ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()

I am currently connecting the interrupt signals to a concat whose output is connected to IRQ_F2P. When the interrupt signals on the axi_uartlite blocks are disconnected, Reset BSP sources does not fail and xparameters.h updates properly

Tags (2)
0 Kudos
5 Replies
dijura
Observer
Observer
621 Views
Registered: ‎09-05-2019

Hi, 

I have the same problem than you. I tried to regenerate the interruption on the PS7 block, but it still fails. Did you reach a solution for this problem?

Thanks, 

Diego 

0 Kudos
marcb
Moderator
Moderator
556 Views
Registered: ‎05-08-2012

Hi @jguenth1 

From the HSI error, I can see that the failure happens in a Tcl foreach statement, where each peripheral with an interrupt port is being accessed. It is looking for an integer, and that looks to be the last argument "$port_intr_id". Based on this information, the concat block is likely causing one of the ports not to have the necessary interrupt ID.

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos
varunbaskar
Visitor
Visitor
372 Views
Registered: ‎03-14-2019

Hello @jguenth1 @dijura 

Did any of you find a solution for this? I'm struggling with the same issue.

Thank you

0 Kudos
marcb
Moderator
Moderator
298 Views
Registered: ‎05-08-2012

Hi @varunbaskar 

Can you try making sure that the interrupt connectivity has the same number of inputs as outputs? The concat block appears to be making a mismatch between the number of inputs and outputs, producing the error. If this does not resolve the issue, please open a new post and include the write_bd_tcl script so that the community can debug further.

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos
dijura
Observer
Observer
89 Views
Registered: ‎09-05-2019

Hi @varunbaskar ,

In my case, the problem came from some signals before the CONCAT lose the condition of Interrupt signals in the properties. 

I had an intermediate block before the CONCAT, an SLICE block,  and the signals are not detected as an interruptions in the Input of the CONCAT. When I delete the SLICE block,  the signals keep the property as Interrupt signa and the problem was solved. 

I'll hope that this information could be useful for you.