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Explorer
Explorer
6,548 Views
Registered: ‎07-28-2008

Right way to shall Microblaze system with logic designer (14.6)?

I created a system to be part of a large teamed FPGA design. When I share my project as a whole, and other member can just copy my system folder and add *.xmp to build the design without issue.

 

But when we put *.xmp through revision control. Simply adding the *.xmp fails in translation, and complains not seeing pcore files, missing nets, ...

 

My guess is: maybe *.xmp has some static file path info which is not updated until a new netlist is generated. Good thing is in the project with checkedout *.xmp, I can open it and regenerate netlist, running now, hopefully it can go through and I will come back update this post.

 

Still it is desirable if netlist regeneration can be skipped, because other members don't know XPS at all.

 

Please comment,

 

Thanks,

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4 Replies
Explorer
Explorer
6,537 Views
Registered: ‎07-28-2008

Re: Right way to shall Microblaze system with logic designer?

Unfortunately, translate fails again.

 

ERROR:ConstraintSystem:59 - Constraint <NET
   "inst_system/inst_mb_system/clk_100_0000MHz"  TNM_NET =
   TNM_mb_main_clk_100MHz;>
   [C:/temp/project/top_level.ucf(410)]: NET
   "inst_system/inst_mb_system/clk_100_0000MHz" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET
   "inst_system/inst_mb_system/ctrl_0_sys_clk_200MHz"	TNM_NET =
   TNM_pcore_clk_200MHz;>
   [C:/temp/project/top_level.ucf(411)]: NET
   "inst_system/inst_mb_system/ctrl_0_sys_clk_200MHz" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:NgdBuild:989 - Failed to process BMM information edkBmmFile.bmm
ERROR:NgdBuild:604 - logical block 'inst_system/inst_mb_system' with
   type 'mb_system' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'mb_system' is not supported in target 'kintex7'.
INTERNAL_ERROR::45 - Memory allocation leak of 112 bytes at 0x38646818 for a 'AddressMappingType' record.
INTERNAL_ERROR::45 - Memory allocation leak of 43 bytes at 0x38DB62C0 for a StrNew.
INTERNAL_ERROR::45 - Memory allocation leak of 88 bytes at 0x386E7048 for a 'AddressMapType' record.
INTERNAL_ERROR::45 - Memory allocation leak of 40 bytes at 0x39C55378 for a 'symbol_context' record.
INTERNAL_ERROR::45 - Memory allocation leak of 36 bytes at 0x38DB6C50 for a StrDup.
INTERNAL_ERROR::45 - Memory allocation leak of 16 bytes at 0x38DB6EB0 for a 'DataFileNameListType' record.
INTERNAL_ERROR::45 - Memory allocation leak of 24 bytes at 0x38DB5D38 for a 'AddressSpaceLinkType' record.
INTERNAL_ERROR::45 - Memory allocation leak of 96 bytes at 0x386E7110 for 'void *' data.

 Please comment,

 

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Explorer
Explorer
6,502 Views
Registered: ‎07-28-2008

Re: Right way to shall Microblaze system with logic designer?

I've tried starting fresh ISE and XPS. In the new ISE project, adding source *.xmp from the design archive folder compiled without any issue.

 

Tomorrow, will start over the real project and retry from step zero.

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Explorer
Explorer
6,488 Views
Registered: ‎07-28-2008

Re: Right way to shall Microblaze system with logic designer?

Just to update, I've started with a working local archive and deleted remote_source folder, manually update all the references. Deleted *.xmp, so the xps project generation .tcl can be triggered. It compiled.

 

Starting new ISE doesn't work, with similar error in original post.

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Xilinx Employee
Xilinx Employee
6,451 Views
Registered: ‎08-02-2007

Re: Right way to shall Microblaze system with logic designer?

Hi,

 

There might be a hierarchy mis-match in the UCF and hence you are seeing these errors

 

You should be looking at the netlist hierarchy of the instances after synthesis to figure out the exact name of the instance and make these changes in the UCF.

 

The procedure will be similar to the one mentioned in the edk_ctt http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/edk_ctt.pdf

 

--Hem

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