11-20-2020 01:40 AM
I've got a Microblaze design targeted at a Kintex 7 based board. I've run several test applications (hello world, memtest etc) successfully by running them from BRAM. I now have another application I want to run that is too big to run from BRAM. I'm sure there is some way to run this from DDR but I can't seem to get it to go. I've tried moving the .text section to DDR and leaving the rest from BRAM but when I try to run the application it does nothing.
I've attached a screen grab of my linker and what happens when I attempt to debug the application. It looks like it's not stepping in to the application.
Can anyone offer any advice on what I am missing here? Lots of googling has not come up with a great deal.
11-20-2020 03:08 AM
This is interesting.
Could you not concatenate BRAMs and achieve what you are trying to do?
Accessing DDRs are slow and is generally used for buffering huge amounts of data. For program memory or instruction memory applications, I would play around with multiple BRAMs.
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11-20-2020 06:18 AM
You can use DDR MIG IP and use that in placing all your code in DDR space.
I've tried moving the .text section to DDR and leaving the rest from BRAM but when I try to run the application it does nothing
> You can select all memory segments as DDR memory (it is big enough to hold the software codes)
And as @dpaul24 mentioned you can multiple internal BRAM
11-20-2020 06:33 AM
I've tried adding more BRAM and updated the hardware specification with the updated xsa which I assume updates the .bit file as well. It didn't help making me wonder if it had updated. Is there anyway to tell from Vitis how much BRAM is available to Microblaze?
11-20-2020 06:37 AM
I have seen mention of doing that. I was hoping to avoid involving the flash for now if I can. I thought I should be able to get the application in to DDR without having to go down that route.
11-20-2020 06:39 AM
I've got 2 separate DDRs available to me that i'm hooked to via MIG. I've ran a memory test on those and they are working just fine.
I tried moving all segments to DDR as you suggested but got the same result. It feels to be like the Microblaze isn't jumping to the correct location to find the code to run.
11-20-2020 07:32 AM
If you are using the debugger, then place all sections in the linker to the DDR and they use the debugger to download the ELF to DDR.
If this doesnt work, ie you dont see the expected results. Then the issue could be the DDR. You can create a simple memory test in the Vitis that will test your DDR.
However, if you are looking to use this in the field you would need a static memory (Flash) and a bootloader. The bootloader runs from BRAM, it takes the elf from flash, stores it in DDR and hands off to the DDR. There are template bootloaders in Vitis
11-20-2020 07:51 AM
Debugger = Vitis/SDK/XSCT
If you right click on your application is project explorer view in the debugger, can you select generate Linker script and place all section to DDR?
Are yo are to do this? If not, then your may not have the Instruction and data busses on the Microblaze connected to the DDR via the AXI interconnect?
If you can do this, great.
11-20-2020 12:06 PM
11-23-2020 01:01 AM
No it's not working. I've worked around it for now by increasing the BRAM available but i'd really like to get to the bottom of this as I shouldn't have to sacrifice BRAM when i've got plenty of DDR I could be using. I've attached the address map for the design incase there's anything there that's not correct?