06-14-2018 10:58 PM
I am working one of the Video Processing application project and using the Vivado 2018.1 and SDK 2018.1. The Vivado design contains PS+PL part and targeted board is ZC702. I had to add some image processing IP stage by stage. Instead of create new project again, I copied the base design and added some image processing IP.After i regenerated bit stream, the HW was imported into SDK to develop application.
All the design has same TPG path.
The base design , base design1 and base design2 was working fine.
But i am facing some issues in the base design3 and base design4.
If i download the bit stream and .elf of the base design3 or base design4 into the board, there was no video output on the monitor.but in UART console I2C init and I2C Transaction is fine and Video IP init and configuration is fine.
But if i download the bit stream of the base design3 and base design4, and the .elf of the base design , base design1 and base design2, the design was working fine without any issue.
If i download the bit stream of the base design ,base design1 and base design2 and the .elf of the base design3 and base design4, the design wasn't working.
It seems that the base design3 and base design4 has building issue.
I have done only small changes between this base designs.
what could be a problem?
06-18-2018 12:42 AM
06-20-2018 04:11 AM
In the block design ,
ctrl_clk is a AXI Lite clock (50MHz)
clk200 is a VDMA Clock (200MHz)
pclk_0 is a pixel clock (8MHz) of the camera
vid_out_clk is a video resolution clock (which depends on the output resolution) . Ex : For HD resolution (74.25MHz)
core_clk is video processing clock to all Video Processing IP.