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stgateizo
Explorer
Explorer
14,455 Views
Registered: ‎10-07-2016

SDK banned from Vivado 2019.2 ???

Dear Xilinx community,

does anybody know the reason why Xilinx has banned the SDK from Vivado 2019.2 ?

To be honest I was shocked, as I read this the first time.

It looks like you have to use Vitis now, although it is brand and does not run very stable under windows. Some functionality is even not supported under Windows...

Why doesn't Xilinx support both paltforms in parallel for a certain time, to make a smoother transition from SDK to Vitis?

It looks like Xilinx has not learned its lessons from the introduction of Vivado, which was also a mess...

Kind regards

Steffen

40 Replies
nigg
Observer
Observer
2,173 Views
Registered: ‎11-26-2012

Dear Xilinx
I must agree with the verdict that "killiing" the SDK just like that is premature and kind of feels irresponsible to your customers. While from experience I know you don't care for customers smaller than 10'000 employee, I still want you to note my dissatisfaction.

arashr
Explorer
Explorer
2,111 Views
Registered: ‎02-06-2018

I also believe that instead of introducing a new brand, you should focus on improving current tools, fixing bugs, increasing the loading and compiling speed, optimizing and making it a smooth experience.

We are also in middle of a MPSoC project. I installed Vitis and ... duh, instead of working on the project, I'm fixing all these random errors.

jrichels20
Visitor
Visitor
1,647 Views
Registered: ‎03-19-2019

Thank you.  2019.1 brings back SDK ?!  2019.2 uninstalling as I write.

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paebbels
Explorer
Explorer
1,542 Views
Registered: ‎04-24-2014

Latest Vivado 2020.1 can still generate sysdef / hdf files. You only get a deprecated warning.

 

create_project -in_memory -part xczu19eg-ffvc1760-1-e
write_sysdef -hwdef ./BlockDesign.hwdef -bitfile ./BlockDesign.bit -file BlockDesign.hdf

 

 

 

 

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JohnHaichao
Newbie
Newbie
1,435 Views
Registered: ‎06-30-2020

This is a good topic of how a company should pay attention to their technical end users. The change in workflow without transition period or backward compatibility would have big impact on engineers' work efficiency. It, in turn, would have big impact on companies' (no matter large or small companies) products development efficiency. In short and long-term, it would have big impact on engineers' decision to choose FPGA products, and no need to say all engineers with hands on the FPGA products share the same concern.

dbabayev
Observer
Observer
1,387 Views
Registered: ‎03-01-2010

So where do I begin?

I am coming out of using 14.7 and now I am stuck here.

I am used to SDK but it will not last again.

Vistis may be a stretch.

What licensing available for Artix 7 100 part with Vitis? Do I need to purchase anything?

I am using that everywhere now.

 

Please advise.

Thanks,

Dmitry

 

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josephwsamson
Visitor
Visitor
1,378 Views
Registered: ‎05-04-2018

You can use Vivado 2019.1.  Free webpack will handle Artix 7 100

 

Joe Samson

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rdb98791
Participant
Participant
855 Views
Registered: ‎03-05-2020

Now that Vitis has been out for a bit, is there an advantage to using it, other than "so you can keep using Xilinx tools?" I've been reclimbing the learning curves for years now: ISE, XPS/EDK, PLB IP, Vivado AXI IP, Vivado, UCF, XDC, SDK, XSCT, tutorials working in some version but not others, figuring out how to automate builds and competently store the projects into configuration management...

Every time I get to the point where I feel like I can just focus on my customer's application, it feels like Xilinx pulls the rug out again. In my FPGA career, I've honestly spent more time fighting the vendor tools than focusing on the end application. Sadly that's not an exaggeration. 

maps-mpls
Mentor
Mentor
742 Views
Registered: ‎06-20-2017

> In my FPGA career, I've honestly spent more time fighting the vendor tools than focusing on the end application. Sadly that's not an exaggeration. 

LOL.  This goes for a lot of tools.  Things that used to be easy in Word 2007 are a total pain in the rear in the latest version of word.  But you know we've all felt the pain you've expressed.

Anyway, Vitis is getting better.  I'm using Vitis 2020.1.  Works great for baremetal, driver, and linux application development.

One issue is Xilinx is in the business of providing universal solutions to problems they don't even know exist yet.  As a consequence, they often have a myriad of paths for the end user of their tools to select from.  But not all paths are equal, and some are much more time consuming than others.  And when you're under the gun of a project schedule, you don't have time to experiment once you find a path that works, even if you suspect there exists a better path.  Trying to figure all of this out on your own can be frustrating.  In this case, training can provide a rapid return on investment.  But training for brand new tools is often unfulfilling and the tools themselves are moving targets from release to release. 

Which is why I chose, if there is a choice, to not be too early of an adopter of new tools.  I don't always have this luxury, but it helps avoid being the unpaid alpha tester.  (Again, I am speaking of all tools, not just Xilinx tools).

But in the case of using Vitis for embedded development, we are finalizing a custom training course, EMBD-88080:  Rapid Development Embedded Design, which evolved out of a desire for more productivity than the existing EMBD-PLNX training provided.  Necessity is the mother of invention.  The real-world labs teach techniques and a path through an embedded development cycle that we have developed over the past couple of months for our day jobs.  The paths are much faster than we've seen in tutorials and official training.  The target audience of this training are engineers on teams that want to spend more time providing solutions to meet their requirements and less time battling tools.  (Though, as we all know, you will still have to battle the tools from time to time.)  It is not intended for college students, for example.   The goal was to provide a mechanism of dozens of design iterations per day, instead of 4 or 5 design iterations per day.  This sort of throughput isn't always necessary, but when it is necessary, it can mean the difference between going home at 5 p.m. with weekends free or going home at 11:00 p.m. and sacrificing your weekends.  We are evaluating whether or not to add a 5th day to tie hardware acceleration of software algorithms within Vitis, i.e., the Vitis Accel flow, and possibly Vitis HLS in a more traditional embedded IP creating flow.  As it is now, we focus on embedded systems design, and Vitis Accel and Vitis HLS requires additional training.  As it is now, the course is shaping up to be the course we wish had existed before we started projects with RFSoC and MPSoC.

*** Destination: Rapid design and development cycles ***
dpaul24
Scholar
Scholar
662 Views
Registered: ‎08-07-2014

@maps-mpls Which is why I chose, if there is a choice, to not be too early of an adopter of new tools. I don't always have this luxury, but it helps avoid being the alpha tester. (Again, I am speaking of all tools, not just Xilinx tools).

Have been using Xilinx tool for about 6 years now. Can't agree more on this!

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

josephsamson
Explorer
Explorer
642 Views
Registered: ‎10-05-2010

I've been designing since Foundation days, so I've seen a lot of updates.

My recent work (camera design) has been with 2018.3, but last week I updated to 2020.2 so that I could use the latest (and now free) MIPI IP. I converted one of my zedboard designs and I had to chase down a few errors, but it wasn't as bad as I feared. I am very careful with Vitis, though. I did have to abandon one workspace because the hardware platform was out-of-date and rebuilding didn't help. I probably clean and build unnecessarily, but I'll figure that out as I get more comfortable. My software needs are pretty simple - a bare metal app, one processor, lwip.

---

Joe Samson