So, I should probably post this to Segger (and I did) but I can't get any sort of meaningful response from them so I thought I would try the Xilinx community and hope for better luck.
We have a custom board with a 7020 on it. We have set it up for 4 bit trace through the EMIO running at 75MHz (trace clock). We do not connect or use the TRACE_CTL signal. We connect the Segger JTrace Pro and their Ozone application to collect trace information and we get nothing. We are using the regular JTAG port (not PJTAG). We can stop and start and single step but no trace information comes out. We don't get the expected half-sync message (0x7fff7fff) but we do see 0x7ffffff. Adjusting the trace sample delays has no effect. Slowing down the trace clock has no effect. I poked around the ETM registers and saw some settings that didn't make sense to me but that might be because I don't know enough about what they should be.
My summary question:
Has anyone successfully used Segger's Ozone/JTrace Pro in combination with a Zynq to collect trace information? If so, what was your secret sauce?
Thanks!
