07-16-2015 02:41 AM
I want to send data from AXILite to AXI Stream with a simple example.The Data are from GPIOs and to DMA. But data transmission failed since the protocols are not the same.I've tried to use protocol converter IP in Vivado but it cannot be used for AXIS. Can anyone tell me what to do next to improve the dataway?
07-19-2015 12:21 AM
07-16-2015 06:55 AM
07-16-2015 06:29 PM
Well, I just want to use GPIO to simulate virtual data input. I've just learned about a little information about DMA and I want to send data(switches' electrical level) to the memory in this way. It fails by just connecting. I want to make a user IP but it also fails.Could you help me?
07-16-2015 09:50 PM - edited 07-16-2015 09:51 PM
Sure, I can help. But this is not the right approach.
If you only want to read switches occasionally, just use the processor to read the GPIO via AXI. No need for DMA. If you need to constantly send data to memory, that's a different story.Trying to hook up GPIO's AXI port directly to the DMA will never work the way you want it to.
07-17-2015 01:09 AM
Er..I mean the second one. The thing that matters is how to convert data into AXI Stream.The IPs in vivado seems not to be helpful in the project.I want to make a custom IP by Verilog but I don't know what to do.
07-17-2015 10:33 AM
The thing that matters is how to convert data into AXI Stream
To be clear, you want to convert data from AXI to AXI stream? Or data from the GPIO to AXI stream?
You could indeed use the AXI DMA or VDMA to convert between AXI and AXI Stream.
07-19-2015 12:21 AM
07-20-2015 12:05 AM
Yeah,I want to solve in this way.However, I don't know how to make a axi stream interface and how to assign values to relevent registers(by just assign values to tdata at each aclk?). I'm trying to make an external on the DMA IP and directly connect it to switches by constraint files but it also fails.Could you help me on the problem with more details?
07-20-2015 10:55 AM
07-21-2015 07:12 PM
Well, I met with troubles writing logics. I create an custom IP with a Master Stream output and make a 8bit input wire pin-out to connect it with switch. I once wanted to change stream_data_out from the generated
stream_data_out <= read_pointer + 32'b1;
stream_data_out <= switch_in;
the simulating result is not good.
Then I directly make the connection by
assign switch_in =m_axis_tdata;
in the top file of my ip, and the Synthesis's OK. However, when I connect it to DMA IP & PS and use xdc file to make pin constraints, Synthesis's OK but Implementation's fails for multi-driver net problems in SWs. I've no ideas what to do next. Is my IP's logic too simple?
07-26-2015 07:23 PM
08-28-2019 05:07 AM
I agree with the other replies in that this is a harder task than you think but if you want a summary I hope this explanation helps. Axis and axi/axilite are completely separate protocols. Axis is a single direction streaming protocol used to send raw data blocks or packets of arbitrary size from one IP to another. It is the designers job to see how the data received is interpreted. Axi and axi lite are used for accessing memory or registers within IPs by sending both the address and the data you want to write or requesting an address and getting a reply with its data. Beneath the hood Axi and axi lite is simply 5 axis channels, read address+metadata (Master to Slave) read data (Slave to Master) write address+metadata (Master to Slave) write data (Master to Slave) and error messages (Master to Slave). The difference between Axi and Axi lite is Axi has more metadata to improve efficiency of large reads/writes. To make a converter first it will only work for writes since Axis is one directional. You need to define a protocol for how you are encoding the data address and metadata in the raw axis datablocks. Only then can you make sense of the data and send out an appropriate Axi write.