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Observer
Observer
12,990 Views
Registered: ‎05-06-2015

Send data from AXI to AXIS

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I want to send data from AXILite to AXI Stream with a simple example.The Data are from GPIOs and to DMA. But data transmission failed since the protocols are not the same.I've tried to use protocol converter IP in Vivado but it cannot be used for AXIS. Can anyone tell me what to do next to improve the dataway? 

 

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Teacher
Teacher
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Registered: ‎03-31-2012
If you are trying to read the gpio & convert it to an axi stream, you need a custom ip. Create an axi-stream master ip with "tools|create_package ip" and add logic to it to read the gpios at the rate you want and send through the master port. Then you can connect it to any stream slave.
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011
This strategy is definitely not going to work for a bunch of reasons. There's no purpose for using the GPIO. AXI Stream is basically just raw data already.

Can you back up and tell us what you're trying to accomplish.
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Observer
Observer
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Registered: ‎05-06-2015

Well, I just want to use GPIO to simulate virtual data input. I've just learned about a little information about DMA and I want to send data(switches' electrical level) to the memory in this way. It fails by just connecting. I want to make a user IP but it also fails.Could you help me?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Sure, I can help. But this is not the right approach.

 

If you only want to read switches occasionally, just use the processor to read the GPIO via AXI. No need for DMA. If you need to constantly send data to memory, that's a different story.Trying to hook up GPIO's AXI port directly to the DMA will never work the way you want it to.

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Observer
Observer
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Registered: ‎05-06-2015

Er..I mean the second one. The thing that matters is how to convert data into AXI Stream.The IPs in vivado seems not to be helpful in the project.I want to make a custom IP by Verilog but I don't know what to do.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Hello,

 

The thing that matters is how to convert data into AXI Stream

To be clear, you want to convert data from AXI to AXI stream? Or data from the GPIO to AXI stream?

 

You could indeed use the AXI DMA or VDMA to convert between AXI and AXI Stream.

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Teacher
Teacher
22,527 Views
Registered: ‎03-31-2012
If you are trying to read the gpio & convert it to an axi stream, you need a custom ip. Create an axi-stream master ip with "tools|create_package ip" and add logic to it to read the gpios at the rate you want and send through the master port. Then you can connect it to any stream slave.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Observer
Observer
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Registered: ‎05-06-2015

Yeah,I want to solve in this way.However, I don't know how to make a axi stream interface and how to assign values to relevent registers(by just assign values to tdata at each aclk?). I'm trying to make an external on the DMA IP and directly connect it to switches by constraint files but it also fails.Could you help me on the problem with more details?

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Teacher
Teacher
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Registered: ‎03-31-2012
Please read my previous posting & try to follow it. It shows how to create the axi-stream master. You need to add logic to read the gpio and send the data out.
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Observer
Observer
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Registered: ‎05-06-2015

Well, I met with troubles writing logics. I create an custom IP with a Master Stream output and make a 8bit input wire pin-out to connect it with switch. I once wanted to change stream_data_out from the generated

  

 stream_data_out <= read_pointer + 32'b1;

to

  

 stream_data_out <= switch_in;

the simulating result is not good.

Then I directly make the connection by

 assign switch_in =m_axis_tdata;

in the top file of my ip, and the Synthesis's OK. However, when I connect it to DMA IP & PS and use xdc file to make pin constraints, Synthesis's OK but Implementation's fails for multi-driver net problems in SWs. I've no ideas what to do next. Is my IP's logic too simple?

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Teacher
Teacher
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Registered: ‎03-31-2012
You need to understand how AXI stream interface works to be able to modify it to do what you want. The changes necessary are more complicated than what you have done so far.
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Visitor
Visitor
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Registered: ‎04-03-2017

I agree with the other replies in that this is a harder task than you think but if you want a summary I hope this explanation helps. Axis and axi/axilite are completely separate protocols. Axis is a single direction streaming protocol used to send raw data blocks or packets of arbitrary size from one IP to another. It is the designers job to see how the data received is interpreted. Axi and axi lite are used for accessing memory or registers within IPs by sending both the address and the data you want to write or requesting an address and getting a reply with its data. Beneath the hood Axi and axi lite is simply 5 axis channels, read address+metadata (Master to Slave) read data (Slave to Master) write address+metadata (Master to Slave) write data (Master to Slave) and error messages (Master to Slave). The difference between Axi and Axi lite is Axi has more metadata to improve efficiency of large reads/writes. To make a converter first it will only work for writes since Axis is one directional. You need to define a protocol for how you are encoding the data address and metadata in the raw axis datablocks. Only then can you make sense of the data and send out an appropriate Axi write. 

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