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Explorer
Explorer
4,856 Views
Registered: ‎05-31-2015

Spartan 6 BRAM read delay

Hello,

                      I am working in Spartan 6 microblaze. In microblaze I have enabled cache for DDR memory access and the segments like .bss lies in the DDR memory. In SDK environment , I started a timer and read a single value from BRAM, got value from timer for eg cnt  and stopped timer . I am getting different values for cnt each time I run program. Why does this happen? The value has to be same since we should take same time period to read a single value from BRAM each time.

 

With Regards

Shalini

 

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3 Replies
Xilinx Employee
Xilinx Employee
4,773 Views
Registered: ‎08-01-2012

Re: Spartan 6 BRAM read delay

Moving this post to "Embedded Systems" forum board by expecting reply posts. 

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Moderator
Moderator
4,709 Views
Registered: ‎09-12-2007

Re: Spartan 6 BRAM read delay

What is the difference? im not sure if this would be deterministic, the DDR access time may differ. Do you see the same behaviour with BRAM?

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Explorer
Explorer
4,695 Views
Registered: ‎05-31-2015

Re: Spartan 6 BRAM read delay

Hello,

 

  Yes. I am seeing different time intervals to read from bram and even from microblaze GPIO port. Why does it happen so?

 

With regards

Shalini

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