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Registered: ‎04-08-2014

Strange toggling of SS in QSPI core

Hi guys,


I have a problem with the Quad SPI core (v 5.1) of Vivado on the Zynq/Zedboard. I have succesfully setup a working QSPI core, data can be transmitted. However at the end of each transmission the chip/slave select pin is toggled for a very short period of time.


my spi transmission procedure:

1. configure SPI core (default, SPI system enabled)

2. write data to DTR (data transmission) register (here 0x0F)

3. clear SPISSR

4. clear master transaction inhibit bit


Then data is transmitted. The resulting waveforms can be seen in the attachment.

Does anyone know, where this toggling comes from?


Thank you!

spi bug.png
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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007

Re: Strange toggling of SS in QSPI core



I have seen this issue. In the behavior i dont see any effect on the functionality of this IP.


Can you please confirm if you are seeing a change in the functionality of the design?



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