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Visitor phytebunk
Visitor
334 Views
Registered: ‎03-26-2019

Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Dear forum,

trying to generate the bitstream for my project I get the "Sub-optimal placement for a clock-capable IO pin and MMCM pair" error. Earlyer I used the FPGA with internal clock (bitstream generation worked fine), now I want to use an external clock via pin C15 (MRCC) and got this error. Unfortunately I wasn't able to solve it on my own.

As the error msg informs about the opportunity using following constraint I expected the problem to be in the belonging net. "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets myBD_i/clk_wiz_0/inst/clk_in1_myBD_clk_wiz_0_0]". So I opened the schematic (see pic below) and inspected the properties for "myclk_50MHz", IBUF and MMCME2_ADV. The clock region was for all three the same: X0Y2. So what could be the problem if they are all in the same clock region?

Thanks!

 

 

plan.PNG

 

Hardware:

-xc7a100tcsg324-1

complete error-msg:

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets myBD_i/clk_wiz_0/inst/clk_in1_myBD_clk_wiz_0_0] >

	myBD_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y125
	myBD_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	myBD_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
	myBD_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	myBD_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
	myBD_i/clk_wiz_0/inst/clkout1_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	myBD_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
	myBD_i/clk_wiz_0/inst/clkout2_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y29

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	myBD_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT2) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
	myBD_i/clk_wiz_0/inst/clkout3_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y28

 

 

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Guide avrumw
Guide
290 Views
Registered: ‎01-23-2009

Re: Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Pin C15 of this device is the N side of an MRCC pair. Only the P side (D15) can be used as a single ended clock capable pin.

This is what is causing your problem.

If you cannot move the pin on your board, you will have to use CLOCK_DEDICATED_ROUTE=FALSE which will result in sub-optimal timing on the clock - notably, any kind of interface that uses this clock as a reference will be significantly harder to get to meet timing.

Avrum

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4 Replies
Teacher drjohnsmith
Teacher
308 Views
Registered: ‎07-09-2009

Re: Sub-optimal placement for a clock-capable IO pin and MMCM pair

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When you created your clock module in the wizard, what input buffer type did you select ?

have you selected a Clock capable input pin to drive the MMCM ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor phytebunk
Visitor
303 Views
Registered: ‎03-26-2019

Re: Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Thanks for your reply. I selected "Single ended clock capable pin" as input and I didn't insert any buffer manually between clock in of the clocking wizard and the input. Should I insert a buffer between Input and Clocking wizard or select e.g. "Global buffer" in the Wizard?

 

 

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Highlighted
Guide avrumw
Guide
291 Views
Registered: ‎01-23-2009

Re: Sub-optimal placement for a clock-capable IO pin and MMCM pair

Jump to solution

Pin C15 of this device is the N side of an MRCC pair. Only the P side (D15) can be used as a single ended clock capable pin.

This is what is causing your problem.

If you cannot move the pin on your board, you will have to use CLOCK_DEDICATED_ROUTE=FALSE which will result in sub-optimal timing on the clock - notably, any kind of interface that uses this clock as a reference will be significantly harder to get to meet timing.

Avrum

View solution in original post

Visitor phytebunk
Visitor
189 Views
Registered: ‎03-26-2019

Re: Sub-optimal placement for a clock-capable IO pin and MMCM pair

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Thank you!
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