I'm running Vivado 2016.2 with a design with two microblazes on a single debug module. I have an SDK project and BSP for each one, and each project generates an ELF while I have verified in simulation to be fine. However, when I go to debug over JTAG, the debug module has the two processors swapped, such that processor A's code runs on processor B and vise versa. Symbols are correct--it's just running on the wrong processor and so the code has trouble doing much useful stuff... I can't seem to find any files I can edit to fix this problem.
My solution so far: Assign the files in the bitstream generation and only be able to load alongside the bitstream, assigning symbol files manually.
Any ideas for how to re-align the exported hardware spec with debug config? I don't know how debug identifies each of the processors.
I did have exactly the same issue and I found out that the microblaze naming does influence the order in which they appear in the hardware description. So the name of microblaze_0 should be alphabetically in front of microblaze_1.