TEMAC on SP601 mapping error in EDK 12.1

[wg]

Hello,

I am trying to implement TEMAC on SP601 board using EDK 12.1. I start in EDK by choosing SP601 Rev C as the board in the BSB. I add TEMAC as a peripheral removing EMACLite and also add timer. I can see that EDK has added certain timing constraints in the ucf for TEMAC. When I try to generate bitstream, I get the following error:

ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of

   the design and/or constraints.

   Unplaced instances by type:

     FF    100 (9.3)

     LUT    12 (1.0)

   Please evaluate the following:

   - If there are user-defined constraints or area groups:

     Please look at the "User-defined constraints" section below to determine

     what constraints might be impacting the fitting of this design.

     Evaluate if they can be moved, removed or resized to allow for fitting.

     Verify that they do not overlap or conflict with clock region restrictions.

     See the clock region reports in the MAP log file (*map) for more details

     on clock region usage.

   - If there is difficulty in placing LUTs:

     Try using the MAP LUT Combining Option (map lc area|auto|off).

   - If there is difficulty in placing FFs:

     Evaluate the number and configuration of the control sets in your design.

Then it lists the FFs and LUTs that are having problems and then it gives another error.

ERROR:Place:120 - There were not enough sites to place all selected components.

   Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If

   you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try

   again

I tried using the “xe –c” option during map and PAR phase and making the XIL_PAR_ENABLE_LEGALIZER variable to 1. But then after generating the netlist, the generating bitstream process was still not finished even after 2 hrs. So I stopped it.

Now, the question is why I am getting an error in compiling a system created by BSB wizard for the SP601 board? Has anybody else faced this problem? How do I resolve this issue?

Regards,

wg

[mamisadegh2 · Accepted solution]

Dear wg,

I dont really know what is the solution to your problem however i give you my guess,

from what you say, your FPGA device is not large enough to provide required number of slieces by TEMAC module.

As you know TEMAC is a very resource consuming and very large module and it requires a large number of FFs and LUTs. It seems that your Base System is so large that your device has no more free space for TEMAC.

My suggestion:

1- double check the options you have set for TEMAC module, try to uncheck all of the extra options, for example if hardware checksum is active disable it.

2- have an overal look as your base system and omit those modules that you feel are not really necessary.

wg, it is obvious , when your device gets full, the place and route process and achieving into required timing constraints gets harder. higher device utilization directly results more effort for PAR engine to meet constrains. so if it has took you 2 hours, it is natural.

[wg]

Hello mamisadegh2,

Thanks for your reply. I will turn off the hardware chksum in TEMAC, remove the unnecessary modules added by the BSB and give it a try. I guess I expected the device on the SP601 board to have the capacity to implement TEMAC at it's full potential, that's why the question.

Regards,

wg

[wg]

Hello mamisadegh2,

I removed the unnecessary peripherals added by BSB and it compiled. I didn't have to remove the h/w chksum.

Thanks,

wg