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Scholar
Scholar
12,707 Views
Registered: ‎11-21-2013

The 2015.4 SDK does not build BSP - internal error

Hello,

 

The 2015.4 SDK does not build BSP on a design that has no issues with the 2015.2

 

We usually run through XSCT in batch/tcl mode, and then follow up with 'make' on Makefile, also in batch mode. Never had issues on 2015.2

 

When we try to do this through GUI, the SDK reports "Internal Error" and a message that is pasted below.

 

We will not be migrating to 2015.4 unless we will find a workaround for another, completely different, issue (CR submitted for place_design on that) but I would like to share the bit/bmm/hdf files with Xilinx to chase this SDK issue. Feel free to send me the EZMove link for that.

 

Thank you

Vlad

 

12:19:05 INFO    : Launching XSDB server: xsdb -n /opt/Xilinx/SDK/2015.4/scripts/xsdb/xsdb/xsdb-server.tcl
12:19:06 INFO    : XSDB server has started successfully.
12:19:07 INFO    : Restoring local repository preferences:
         /home/IGNIS/vmuravin/projects/orchestra/sdk/sdk_trunk/sdk_drivers
12:19:09 ERROR    : (XSDB Server)ERROR: [Hsi 55-1580] This v2_1_0 is not valid driver as it doesn't contain data folder

12:19:09 ERROR    : Internal error. Unable to add /home/IGNIS/vmuravin/projects/orchestra/sdk/sdk_trunk/sdk_drivers as a repository.
12:21:43 ERROR    : (XSDB Server)ERROR: [Common 17-161] Invalid option value '{} inst_intc_mba' specified for 'object'.

12:21:43 ERROR    : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_intc_v3_4::generate : ERROR: [Common 17-161] Invalid option value '{} inst_intc_mba' specified for 'object'.

    while executing
"common::get_property IP_NAME $intc_periph"
    (procedure "::hsi::utils::get_interrupt_id" line 40)
    invoked from within
"::hsi::utils::get_interrupt_id $t_ip_name $source_pin"
    ("foreach" body line 19)
    invoked from within
"foreach source_pin $source_pins {
        #default value as per external processor
        set t_source_port_name          [common::get_property NAME ..."
    (procedure "intc_update_source_array" line 21)
    invoked from within
"intc_update_source_array $periph"
    (procedure "intc_define_vector_table" line 15)
    invoked from within
"intc_define_vector_table $periph $config_inc $tmp_config_file"
    ("foreach" body line 28)
    invoked from within
"foreach periph $periphs {
        set periph_name [string toupper [get_property NAME $periph ]]
    set xpar_periph_name [::hsi::utils::format_xparam_nam..."
    (procedure "intc_define_config_file" line 30)
    invoked from within
"intc_define_config_file $drv_handle $periphs $config_inc"
    (procedure "::sw_intc_v3_4::generate" line 52)
    invoked from within
"::sw_intc_v3_4::generate inst_intc_mba"
ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()

12:21:43 ERROR    : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp.

12:21:43 ERROR    : Error generating bsp sources: Failed in generating sources
12:21:43 ERROR    : Failed to generate sources for BSP project standalone_bsp_0
org.eclipse.core.runtime.CoreException: Internal error occurred while generating bsp sources. Please check the SDK Log view for further details.
    at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.internalGenerateBsp(RegenBspSourcesHandler.java:178)
    at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.access$2(RegenBspSourcesHandler.java:163)
    at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1$1.run(RegenBspSourcesHandler.java:131)
    at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2345)
    at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1.run(RegenBspSourcesHandler.java:135)
    at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:121)

Vladislav Muravin
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11 Replies
Highlighted
Scholar
Scholar
12,668 Views
Registered: ‎09-05-2011

Hi Vlad,

Can you attach the workspace where you see this problem?

Thanks.

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Highlighted
Scholar
Scholar
12,555 Views
Registered: ‎11-09-2013

i know this is not you want to hear but:

 

can you test the same thing on windows PC ?

 

we have 0, I repeat 0 issues with 2015.4 on Win PC

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Observer
Observer
11,496 Views
Registered: ‎01-05-2016

Hi 

I have the same problem, I generate a microblaze design on vivado 2015.4 and generated the bitstream, I exported it to SDK to be able to load FreeRTOS, but when I try to create FreeRTOS_bsp an error burst :" Failed to generate sources for bsp " 

 
Images intégrées 1
 
and SDK log window contains:
 
15:53:07 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_intc_v3_4::generate : can't read "source_name(1)": no such element in array
    while executing
"string compare -nocase $source_name($i) "system""
    ("foreach" body line 17)
    invoked from within
"foreach periph $periphs {
        #update global array of Interrupt sources for this periph
        intc_update_source_array $periph
 
        lappend ..."
    (procedure "xredefine_intc" line 17)
    invoked from within
"xredefine_intc $drv_handle $file_handle"
    (procedure "xdefine_canonical_xpars" line 71)
    invoked from within
"xdefine_canonical_xpars $drv_handle "xparameters.h" "Intc" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C..."
    (procedure "::sw_intc_v3_4::generate" line 57)
    invoked from within
"::sw_intc_v3_4::generate microblaze_0_axi_intc"
 
15:53:07 ERROR : (XSDB Server)ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
ERROR: [Hsi 55-1450] Error: running generate_bsp.
 
15:53:07 ERROR : Error generating bsp sources: Failed in generating sources
15:53:07 ERROR : Failed to generate sources for BSP project freertos823_xilinx_bsp_4
org.eclipse.core.runtime.CoreException: Internal error occurred while generating bsp sources. Please check the SDK Log view for further details.
at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.internalGenerateBsp(RegenBspSourcesHandler.java:178)
at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler.access$2(RegenBspSourcesHandler.java:163)
at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1$1.run(RegenBspSourcesHandler.java:131)
at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2345)
at com.xilinx.sdk.sw.ui.handlers.RegenBspSourcesHandler$1.run(RegenBspSourcesHandler.java:135)
at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:121)
 
 

Help please I'm stuck here , what should I do ??

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Highlighted
Scholar
Scholar
11,475 Views
Registered: ‎09-05-2011

How does you hardware look like?

There is a known issue in SDK 2015.4 when generating FreeRTOS BSP with SOCKET_API lwIP library but not when using RAW_API.
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Observer
Observer
11,418 Views
Registered: ‎01-05-2016

Hi

My work space is in the link bellow (I tryed to generate FreeRTOS_bsp with vivado 2014.2 and 2014.4 and 2015.4 as well but always the same problem) .  Please help, I spent more than two weeks searching a sollution to this problem.

Link: https://drive.google.com/open?id=0BzA3AgdZHzRpMlR2OG43bzBNbUk

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Visitor
Visitor
10,625 Views
Registered: ‎10-21-2011

Hi s_zo and others,

 

I have been struggling with the same exact errors for several weeks now and have just discovered what was causing the problem and an easy workaround. My BD (and overall FPGA design) had previously worked fine when exporting to SDK in Vivado 2015.1, but now fails with this same error in 2015.4. This is what I get after exporting the HW design, launching SDK, and then trying to build my BSP (or create a new BSP from scratch), even on a brand new workspace environment:

 

20:42:46 ERROR      : (XSDB Server)ERROR: [Common 17-161] Invalid option value '{} axi_intc_0' specified for 'object'.

ERROR: [Hsi 55-1545] Problem running tcl command ::sw_intc_v3_4::generate : ERROR: [Common 17-161] Invalid option value '{} axi_intc_0' specified for 'object'.

 

    while executing

"common::get_property IP_NAME $intc_periph"

    (procedure "::hsi::utils::get_interrupt_id" line 40)

    invoked from within

"::hsi::utils::get_interrupt_id $t_ip_name $source_pin"

    ("foreach" body line 19)

...

 

ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()

20:42:46 ERROR      : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp.

20:42:47 ERROR      : Error generating bsp sources: Failed in generating sources

 

 

In my case, I tracked the problem to 3 interrupt signals in my BD which were going both to the microblaze interrupt controller (axi_intc_0) AND an external port (for use in my top-level Verilog file). I found that if I removed these signals from the external ports while leaving them connected to the interrupt controller, everything worked fine and SDK would build the BSP without error. When I put even one of these signals back in (any one, it didn't matter), I would be back to this same error in SDK. As a test, I registered the 3 interrupt signals going to the external port using the Utility Register IP block in IPI, while leaving the primary interrupt signals going directly to the axi_intc block without the extra register delay, and ... voila! It now works fine, goes through the full tool-flow and I can now again build the BSP in SDK without error.

 

The only downside was an extra clock-cycle delay on these 3 signals going to my external logic. However, this exact timing was not critical in my case.

 

An interesting side note: registering these signals inside my top-level Verilog file before use elsewhere (but outside my BD design) did nothing to fix the problem, even though this is theoretically the same thing after synthesis. However, since creation of the BSP relies only upon what is inside the BD ... it just did not like me using the signals I use as interrupt sources in other places outside of the BD directly.

 

I don't know if your situation was similar (routing some internal interrupt signals also to an external port), or unrelated ... but it seems to me like something changed in the back-end TCL scripts during the tracking/enumeration of interrupt signals going to the interrupt controller (to create xparameters.h ?), that is causing other things that once worked to suddenly stop working. If your situation is different, I would encourage you to inspect all of your interrupt sources and look for something out of the ordinary (like going to an external port, width mismatches in the "Concat" block, or possibly to another IP block?) and see if you can get the problem to go away with some trial and error to narrow it down. Then perhaps something as simple as adding a register to the other path will mitigate the problem. I hope this helps.

 

- KP

 

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Highlighted
Observer
Observer
10,553 Views
Registered: ‎01-05-2016

Hi KP,

 

Yes it was, I found it last week (a connection between intr timer and the concat IP is missing), every thing work fine at the moment.

Thank you

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Highlighted
Visitor
Visitor
9,318 Views
Registered: ‎07-07-2016

Hello s_so
I meet the similar problem too.
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Highlighted
Visitor
Visitor
9,313 Views
Registered: ‎07-07-2016

Hello s_zo

I meet the simiar problem too.And I dont konw how to do with it.I will show the SDK.log below:

 I hope you can help me with this problem.The tool I'm using is Vivado15.2.1 .

QQ图片20160708143733.jpg
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Highlighted
Observer
Observer
6,257 Views
Registered: ‎01-05-2016

Hi small_ma

 

If you have interrupts in your design be sure that all of them are connected to "concat" IP and then if necessary to Axi _interc.

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Highlighted
Xilinx Employee
Xilinx Employee
6,236 Views
Registered: ‎08-01-2008

check this ARs
http://www.xilinx.com/support/answers/51574.html
http://www.xilinx.com/support/answers/62472.html
http://www.xilinx.com/support/answers/51613.html
https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2014-3-Simulation-Error/td-p/541155
Thanks and Regards
Balkrishan
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