Timing errors when changing a clock from an external to internally generated signal.
I've been working on a ppc based design for a virtex 4 fpga in EDK 9.2, and up until this week I've had a clock for one of my IP coming in on one of the gclk pins. This setup generated no timing errors, although there wasn't a whole lot of margin for some signals. Earlier this week however, I was informed that the signal actually needed to be generated internally, so I started using a DCM to produce it. Without changing anything other than the source of the clock, all of the sudden I was getting over 200 timing errors, some by as much as 7 ns. I even reduced the clock from 200MHz to 150Mhz, but it still is generating tons of timing errors. Additionally, two of my other clock domains which are generated by different DCMs also started having errors.
Anyway, I've simplified some of the logic and removed a few optional portions, but it still doesn't route properly. I'm not even sure why it became a problem all of the sudden. Is there anything I can do fix or reduce the extent of the problem? Also, does anyone know of any documentation explaining why using the DCM instead of a buffered external clock would cause this sort of problem even though the frequency was the same, or even lower?
Is it possible you're trying to use the output of the DCM without a BUFG or BUFGMUX? This would create all sorts of problems due to clock routing skew. Depending on how you instantiated the DCM you may need to instantiate the BUFG as well. Normally when using a DCM the buffered output of the BUFG drives all clock loads including the feedback input of the DCM.