Hello Ash80,
Unfortunately, Verilog is not my strong point :-( however, I should think that instantiation of an IOBuf should be a guaranteed way to make sure that the tools use this primitive.
However, the Language templates in ISE suggest the following as an example on how to instantiate the primitive:
// IOBUF : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (IOBUF_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.
// <-----Cut code below this line---->
// IOBUF: Single-ended Bi-directional Buffer
// All devices
// Xilinx HDL Language Template, version 9.1.3i
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only)
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(O), // Buffer output
.IO(IO), // Buffer inout port (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);
// End of IOBUF_inst instantiation
Hope that helps!
Kris Chaplin
Xilinx UK
