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Visitor ash80
Visitor
10,904 Views
Registered: ‎09-26-2007

To test ethernet mac

Hi all,
     I want to test Open core ETHERNET MAC CODE , I used the wb2opb and opb2wb from opencore too. Import the MAC code into edk and interfaced with (wb2opb & opb2wb).I Used sdk (c-code) to  test MAC. Generated Address are:-
 
Analyzing file F:\phy_ethernet\eth2e1_4\eth2e1_phyinterface\executable.elf...
Linker Script generated successfully.
 
Address Map for Processor microblaze_0
  (0000000000-0x00007fff) dlmb_cntlr dlmb
  (0000000000-0x00007fff) ilmb_cntlr ilmb
  (0x40600000-0x4060ffff) RS232 mb_opb
  (0x41200000-0x4120ffff) opb_intc_0 mb_opb
  (0x41300000-0x413fffff) SRAM mb_opb
  (0x41300000-0x413fffff) SRAM microblaze_0_IXCL
  (0x41300000-0x413fffff) SRAM microblaze_0_DXCL
  (0x41400000-0x4140ffff) debug_module mb_opb
  (0x80000000-0x800000ff) opb2wb_0 mb_opb
Address map generated successfully.
 
                                                    I have included  <xio.h>header file in my c-code .
 
                                                   By using XIo_Out i can write data into the MAC Register(using base address 0x80000000) .But I am facing the problem that i cannot read this data by using XIo_In .
 
                                                  But when i write data into SRAM base address(0x41300000) by using (XIo_Out), then i can  read  this data by using (XIo_In) .
 
 
SO,I need your assistance, Eagerly waiting for your response.
 
thanks in advance
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4 Replies
Xilinx Employee
Xilinx Employee
10,868 Views
Registered: ‎08-07-2007

Re: To test ethernet mac

Hello Ash80,
 
It looks like you are trying things the right way, and using the XIo functions to read and write the register.
 
You mention that you are successful in writing to the Opencores mac register using Xio_Out.  Do you have a way of confirming that this write was not successful?  You say that Xio_In does not work in the core range, so how do you know that the core has been written to?
 
If you have a simulator, it would be possible to track down the bus transactions.  I would recommend looking at the following first:
 
Is the core being clocked correctly?  How about the bridge?
Is the reset polarity of the core correct? And the bridge?
 
Are there any other peripherals that you can put on the wb bus to confirm that the bridge is working properly?  Perhaps that will help you narrow down where the problem is.
 
Good luck!
Kris Chaplin
Xilinx UK
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Visitor ash80
Visitor
10,824 Views
Registered: ‎09-26-2007

Re: To test ethernet mac

Hi Chaplin,
   
  I am very thankfull to you that it help me lot to debug. Now another doubt is
 
I am using spartarn-3.
 
and my  logic :-       assign    md_io = md_io_T ? md_io_O : 1'bz;
                                assign md_io_I = md_io;
 
                                         this is generating  one TBUF. And in Spartarn-3 no TBUF is available.Thus to read data from PHY is not being possible.So for bidirectional signal as available in  PHY is MDIO how we implement this by using [md_io_T(enable signal),md_io_O(output signal ),md_io_I(output signal)]we get IOBUF instead of TBUF?I need your help
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Xilinx Employee
Xilinx Employee
10,761 Views
Registered: ‎08-07-2007

Re: To test ethernet mac

Hello Ash80,
 
Unfortunately, Verilog is not my strong point :-( however, I should think that instantiation of an IOBuf should be a guaranteed way to make sure that the tools use this primitive.
 
However, the Language templates in ISE suggest the following as an example on how to instantiate the primitive:
 
//      IOBUF      : In order to incorporate this function into the design,
//     Verilog     : the following instance declaration needs to be placed
//    instance     : in the body of the design code.  The instance name
//   declaration   : (IOBUF_inst) and/or the port declarations within the
//      code       : parenthesis may be changed to properly reference and
//                 : connect this function to the design.  Delete or comment
//                 : out inputs/outs that are not necessary.
//  <-----Cut code below this line---->
   // IOBUF: Single-ended Bi-directional Buffer
   //        All devices
   // Xilinx HDL Language Template, version 9.1.3i
  
   IOBUF #(
      .DRIVE(12), // Specify the output drive strength
      .IBUF_DELAY_VALUE("0"),   // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only)
      .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
      .IOSTANDARD("DEFAULT"), // Specify the I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) IOBUF_inst (
      .O(O),     // Buffer output
      .IO(IO),   // Buffer inout port (connect directly to top-level port)
      .I(I),     // Buffer input
      .T(T)      // 3-state enable input
   );
 
   // End of IOBUF_inst instantiation
 
Hope that helps!
     
Kris Chaplin
Xilinx UK
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Newbie igormohor
Newbie
10,729 Views
Registered: ‎10-02-2007

Re: To test ethernet mac

Hi.

I"m the author of the 10/100 Ethernet MAC IP Core version that is published at Opencores. Let me tell you few facts about it.
The Opencore version has several problems. For non-commercial usage (learning) it is fine. Under heavier traffic it stops responding.
I fixed all problems and sell the commercial license. Besides the problems already mentioned, there are several improvements. One of them is
that the core is already EDK usable. You can import it to your IP library and don't need to do anything any more. The OPB interface is already
in. This version was tested thoroughly in the network that was heavily loaded.

If you're interested, let me know through the private message.

Best regards,
     Igor
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