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Newbie elras2
Newbie
1,900 Views
Registered: ‎01-21-2010

Tri-state ports in custom peripheral

Hello, this is my first post on this board, so I appologise if I don't follow the correct protocol!

 

I'm attempting to implement a custom peripheral in EDK 11.3 which has two bidirectional ports.  The target is a Virtex4 FX part.

 

I've  implemented it using the guidlines in the psf_rm section on the subject, but still seem to have a problem with the implementation. I'll run through the steps I took and the problems encountered and see if anyone has come accross similar problems.

 

(1) I generated the peripheral using the CIP, calling it PPC_IF.

(2) I added the ports I require (Ap1_LB_AD and Ap1_LB_DP) to the ppc_if.vhd file. For the bi-directional ports I included *_I, *_O and *_T signals, as described in the ref man.

(3) I modified the user_logic.vhd file to match

(4) I modified the instansiation ports of user_logic.vhd  in ppc_if.vhd.

(5) I used CIP to import the peripheral to update the *.mpd files. - During this I noticed that in the Port Attributes stage there were two ports called Ap1_LB_AD and two called Ap1_LB_DP, in addition to the *_I, *_O and *_T signals for each. (my understanding is that there should be one of each, not two).  The resulting MPD file also has two copies of these, as shown here:

 

 

PORT Ap1_LB_AD_I = "", DIR = I, VEC = [0:31]
PORT Ap1_LB_AD_O = "", DIR = O, VEC = [0:31]
PORT Ap1_LB_AD_T = "", DIR = O
PORT Ap1_LB_DP_I = "", DIR = I, VEC = [0:3]
PORT Ap1_LB_DP_O = "", DIR = O, VEC = [0:3]
PORT Ap1_LB_DP_T = "", DIR = O
 

PORT Ap1_LB_AD = "", DIR = IO, VEC = [0:31], TRI_O = Ap1_LB_AD_O, TRI_T = Ap1_LB_AD_T, TRI_I = Ap1_LB_AD_I, THREE_STATE = TRUE
PORT Ap1_LB_DP = "", DIR = IO, VEC = [0:3], TRI_O = Ap1_LB_DP_O, TRI_T = Ap1_LB_DP_T, TRI_I = Ap1_LB_DP_I, THREE_STATE = TRUE
PORT Ap1_LB_AD = "", DIR = IO, VEC = [0:31], TRI_O = Ap1_LB_AD_O, TRI_T = Ap1_LB_AD_T, TRI_I = Ap1_LB_AD_I, THREE_STATE = TRUE
PORT Ap1_LB_DP = "", DIR = IO, VEC = [0:3], TRI_O = Ap1_LB_DP_O, TRI_T = Ap1_LB_DP_T, TRI_I = Ap1_LB_DP_I, THREE_STATE = TRUE

(6) I added the peripheral to the design and looked at the ports tab of the system assemply vew to attach the signals to external signals.  - I was supprised at this point to notice that there are now FOUR ports called Ap1_LB_AD and four Ap1_LB_DP ports!

 

I've tried removing the peripheral from the sytem, cleaning the project, rescanning user repositories and adding the peripheral back into the system, but the problem remained.

I would like to know if anyone has come accross this problem before and what I need to do to solve it.

 

Thanks

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