04-29-2008 08:30 AM
I would like to send the System clock out of the Microblaze submodule. I tried making the clock_generator_0 port CLK_OUT0 sys_clk_s net a external port.
I receive the following error.
Make instance clock_generator_0 port CLKOUT0 external with net as port name
Can't make external port sys_clk_s_pin - net sys_clk_s already used
I think this is because the net is used all over the place and the port name may not be the same name as the signal. How can I send the clock to a external output port?
04-29-2008 10:36 AM
Do you want the "external" clock to be external to the FPGA (brought to an I/O pin) or external to the MicroBlaze module but still inside the FPGA?
04-29-2008 10:56 AM
Still inside the FPGA but outside the Microblaze Submodule. I would also want to send out a Reset Signal.
04-29-2008 11:44 AM
Are you trying to connect the output of the clock generator as an external port?
04-29-2008 12:17 PM
Yes, I am looking for a way to feed external logic not part of the Microblaze system. but where a Microblaze submodule would share the system clock and reset with
04-29-2008 12:30 PM
You can manually add it to the MHS
PORT sys_clk_s_pin = sys_clk_s, DIR = O