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Visitor nivassi
Registered: ‎07-28-2010

Two clock generators driven by the same CLKIN

Hi all,


I have the following issue. (tool: EDK 14.1)

I have a single clock source feeding a Spartan6 device. I am using a clock generator to generate the clocking resources for my processor system (bus, processor, MPMC).

Then I need another clock generator to generate various clocks for my rest of the system (driving ODDR, peripherals etc).


First approach is to use the system clock generator and generate additional clocks. The design cannot be placed due to  conflicting MCB and pin-loc constraints.

Second is to drive a second clock generator, feeding it with the same clock source as the system clock generator. Again the design cannot be placed due to the same constraints.

Third approach is to generate a clock from the system clock generator and drive with this the input of the second clock generator. This way the design is implemented and all constraints are met.


Although I am happy with this I would like to ask if you can think of any problem with this approach. In addition, how EDK is handling this approach? What clock network is being instantiated?


Thank you in advance,


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Mentor hgleamon1
Registered: ‎11-14-2011

Re: Two clock generators driven by the same CLKIN

You haven't mentioned what part you are using.


How many clocks do you actually NEED in your design? Two clock generators can produce a lot of clocks (device dependant).


To your actual question - I don't believe that there is a general problem with cascading clock generators (although there probably is if you are trying some unusual combination of DCM and PLL, for example). If your simulations match your expectations, your design meets timing and the tools are otherwise happy, then I don't see a problem.


My approach would be to try and rationalise the clocks you want and ensure that they are buffered correctly. Perhaps you could attach a diagram showing your intended design?






"That which we must learn to do, we learn by doing." - Aristotle
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