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Observer
Observer
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Registered: ‎03-29-2019

UART 16550 modification for half duplex

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Hello, i trying to establish a connection with RS485 interface by using Xilinx's IP core UART16550 in my design. Transmission works well except that RTSn signal generated by this block stay active too long, that doesn't allow me to receive response from the connected serial device after a short period of time. I know that this IP core works in full-duplex mode, but maybe there is a way to modify .vhd that there is some kind of active signal only enable when data is being transferred (or a little bit before this transmission), for example by changing logic of OUT1n or OUT2n user signals. I saw similar functionality in modified UARTlite IP by forum's user (UARTlite_RS485) and it works, but in my case i need to use UART16550. So can you help me to understand how to implement this feature in this IP core (or, perhaps, someone has already done this and can share sources or something else).

Regards,
crepe.

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crepe
Observer
Observer
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Registered: ‎03-29-2019

Okay, i am think i did this. For whose that searching for same functionality of UART16550, i put my final .vhd file here. Make backup (!) of original ip core file (C:\Xilinx\Vivado\2018.3\data\ip\xilinx\axi_uart16550_v2_0\hdl\axi_uart16550_v2_0_vh_rfs.vhd) before replacing it (Vivado 2018.3).

I changed logic of 'out1n' signal so use it to control external serial devices instead of 'rtsn'. To allow reception, connect this signal through inverter with 'ctsn'. Also i added waiting stages (1 bit long each) before start bit and after stop bit. I tested UART transmittion with serial device with RS485 and seems like all works well. 

Let me know if something works wrong.

Regards,

crepe

View solution in original post

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crepe
Observer
Observer
511 Views
Registered: ‎03-29-2019

Okay, i am think i did this. For whose that searching for same functionality of UART16550, i put my final .vhd file here. Make backup (!) of original ip core file (C:\Xilinx\Vivado\2018.3\data\ip\xilinx\axi_uart16550_v2_0\hdl\axi_uart16550_v2_0_vh_rfs.vhd) before replacing it (Vivado 2018.3).

I changed logic of 'out1n' signal so use it to control external serial devices instead of 'rtsn'. To allow reception, connect this signal through inverter with 'ctsn'. Also i added waiting stages (1 bit long each) before start bit and after stop bit. I tested UART transmittion with serial device with RS485 and seems like all works well. 

Let me know if something works wrong.

Regards,

crepe

View solution in original post

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