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Observer
Observer
8,296 Views
Registered: ‎05-05-2008

URGENT - Bitstream Generation Errors

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Hi,

I have another problem: On bitstream generation EDK10.1 give 3 errors (YOU CAN HELP ME, PLEASE???):


ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component is placed at site
. The IO component is placed at site . This will not allow
the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this
design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and
allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor
timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs
used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override
this clock rule.
< NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component is placed at site
. The IO component is placed at site . This will not allow
the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this
design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and
allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor
timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs
used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override
this clock rule.
< NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:962 - A DCM / BUFGCTRL clock component pair have been found that are not placed at an optimal DCM / BUFGCTRL
site pair. The DCM component is locked to site and the corresponding
BUFGCTRL component is locked to site . This will not
allow the usage of the fast path between the DCM and the Clock buffer. If this sub optimal condition is acceptable
for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to
very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the
COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< PIN "dcm_0/dcm_0/Using_Virtex.DCM_INST.CLK2X" CLOCK_DEDICATED_ROUTE = FALSE; >

Phase 4.2 (Checksum:994a8f) REAL time: 24 secs

REAL time consumed by placer: 24 secs
CPU time consumed by placer: 20 secs
Total REAL time to Placer completion: 24 secs
Total CPU time to Placer completion: 20 secs

make: *** [__xps/system_routed] Error 1


Thanks

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Participant
Participant
9,124 Views
Registered: ‎05-09-2008

Hi,

 

Sorry but for my several of my designs, I've got these kind of routing error (in ISE10.1, Xilinx hase removed usage of XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING variable) and CLOCK_DEDICATED_ROUTE constraint has solved the problem. So may be it's another problem ?

I don't understand which constraint is not met in your answer (any other error message ?).

 

Best regards. 

View solution in original post

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Participant
Participant
8,284 Views
Registered: ‎05-09-2008

Hi,

 

Why not follow what it's written ?

 

Simply add to your ucf file: 

NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;

NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;

PIN "dcm_0/dcm_0/Using_Virtex.DCM_INST.CLK2X" CLOCK_DEDICATED_ROUTE = FALSE;

 

And it will work.

 

Regards. 

 

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Observer
Observer
8,274 Views
Registered: ‎05-05-2008

Hi,

 

    Yes, I followed what was writen, but on constrains 2 constraints not met... Can you resolve this!?...

 

    Best regards

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Highlighted
Participant
Participant
9,125 Views
Registered: ‎05-09-2008

Hi,

 

Sorry but for my several of my designs, I've got these kind of routing error (in ISE10.1, Xilinx hase removed usage of XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING variable) and CLOCK_DEDICATED_ROUTE constraint has solved the problem. So may be it's another problem ?

I don't understand which constraint is not met in your answer (any other error message ?).

 

Best regards. 

View solution in original post

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