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Visitor amolgole
Visitor
1,484 Views
Registered: ‎11-10-2010

Unable to extract TXOUTCLK from axi_ethernet ip

I am using ISE 13.1.

I have instantiated a microblaze with an axi ethernet ip (v2.01a) configured for SGMII. I have attached the MGTCLK_P/_N ports to the ref clk IOB pins. I want to use this 125MHz clock for clocking things in the fpga fabric. This is done routinely as shown as an example in UG336, pg133, figure 3-4 (TXOUTCLK Drives TXUSRCLK2 (1-Byte Mode)). 

 

In order to do this I copied the axi_ethernet_v2_01_a directory from the install pcores directory to my local project pcores directory. I modified v6_temac_wrap.vhd such that clk125 (=TXOUTCLK after BUFG) is connected the entity port list. I also modified axi_ethernet.vhd to connect the clk125 to its entity port list. I modied the .mpd file to add the clk125 to the port list of the axi_ethernet ip and this worked fine. In EDK I connected this clk125 to an external port so that I could access it outside of the microblaze.

 

Synthesis seems to work fine. But in Translate I get an warning that the clk125 has no driver and subsequently Map fails. 

 

Anyone have any ideas?

 

-Amol

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