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patcher33
Participant
Participant
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Registered: ‎02-01-2018

Updatemem makes NOTHING

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Hello,

 

updatemem in 2017.3 seems to ignore all arguments and makes nothing.

It is a log output:

#-----------------------------------------------------------
# updatemem v2017.3 (64-bit)
# SW Build 2018833 on Wed Oct  4 19:58:22 MDT 2017
# 
# Start of session at: Wed Jan 31 22:56:12 2018
# Process ID: 7120
# Current directory: C:/FPGA/fm1_17.3/fpga/E23_ZX1PE1
# Command line: updatemem.exe -mode batch -source C:/hwdt/Xilinx/SDK/2017.3/scripts/updatemem/main.tcl -notrace -tclargs -meminfo data_rom.mmi -data test_rom.mem -proc dummy -bit system_top.bit -out e23.bit -force -debug
# Log file: C:/FPGA/fm1_17.3/fpga/E23_ZX1PE1/updatemem.log
# Journal file: C:/FPGA/fm1_17.3/fpga/E23_ZX1PE1\updatemem.jou
#-----------------------------------------------------------
source C:/hwdt/Xilinx/SDK/2017.3/scripts/updatemem/main.tcl -notrace

and the same in the journal.

I would await "Loading bitfile ..." and so on - but it makes nothing, also no error reports.

 

Any ideas?

 

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patcher33
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Participant
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Registered: ‎02-01-2018

write_mmi.tcl seems to produce a wrong MMI file.

After the manual modification of the MMI file, the RAM content update works as desired. The correct MMFile for my design:

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="/CPU/processing_system7_1">
  <AddressSpace Name="data_rom" Begin="1073741824" End="1073750015">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X2Y25">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X3Y25">
          <DataWidth MSB="31" LSB="18"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
	</AddressSpace>
  </Processor>
<Config>
  <Option Name="Part" Val="xc7z030fbg676-2"/>
</Config>
</MemInfo>

 updatemem output:

updatemem -mode batch -meminfo data_rom.mmi -data test_rom.mem -proc /CPU/processing_system7_1 -bit system_top.bit -out output.bit -force -debug

****** updatemem v2017.3.1 (64-bit)
  **** SW Build 2035080 on Fri Oct 20 14:20:01 MDT 2017
  **** IP Build 2034413 on Fri Oct 20 15:56:25 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source C:/hwdt/Xilinx/Vivado/2017.3/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo data_rom.mmi -data test_rom.mem -proc /CPU/processing_system7_1 -bit system_top.bit -out output.bit -force -debug

Dump the BRAM Initialization Strings.
Loading bitfile system_top.bit
Loading data files...
Updating memory content...
Creating bitstream...
Writing bitstream output.bit...
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
update_mem completed successfully
update_mem: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 522.543 ; gain = 468.465
INFO: [Common 17-206] Exiting updatemem at Tue Feb  6 08:30:51 2018...

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4 Replies
ibaie
Xilinx Employee
Xilinx Employee
1,855 Views
Registered: ‎10-06-2016
Hi @patcher33,

What does mean do nothing? I mean does it get's stuck or not output file generated?

Regards,
Ibai

Ibai
Don’t forget to reply, kudo, and accept as solution.
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stephenm
Xilinx Employee
Xilinx Employee
1,847 Views
Registered: ‎09-12-2007
Can you share the mmi? How was the mmi created?
Why are you using the -proc as dummy, this should match the instpath in the mmi.


Does the mem data fall within the address range pointed to by the -proc?

You mem should have something like
@0
deadbeef

So updatemem will look in mmi for a valid range.

So, check the -proc matches the instpath, and check mem data falls within region in your mmi
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patcher33
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Registered: ‎02-01-2018

you are right - "-proc dummy" was wrong. I changed it to /CPU/processing_system7_1, but updamemem still makes nothing.

 

the MMI file was created by write_mmi.tcl from Xilinx web page. MMI content:

It is the MMI file:

 

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="/CPU/processing_system7_1">
  <AddressSpace Name="data_rom" Begin="0" End="8191">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X2Y31">
          <DataWidth MSB="31" LSB="18"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
  </Processor>
<Config>
  <Option Name="Part" Val="xc7z030fbg676-2"/>
</Config>
</MemInfo>

As i can see the "AddressSpace" of the AddressRange both begins at 0, but the physical address of the AXI-BRAM controller is 0x40000000. The entries in the MEM files begin also @0.

 

Is it OK?

 

 

 

 

 

 

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patcher33
Participant
Participant
2,264 Views
Registered: ‎02-01-2018

write_mmi.tcl seems to produce a wrong MMI file.

After the manual modification of the MMI file, the RAM content update works as desired. The correct MMFile for my design:

<?xml version="1.0" encoding="UTF-8"?>
<MemInfo Version="1" Minor="0">
  <Processor Endianness="Little" InstPath="/CPU/processing_system7_1">
  <AddressSpace Name="data_rom" Begin="1073741824" End="1073750015">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X2Y25">
          <DataWidth MSB="17" LSB="0"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X3Y25">
          <DataWidth MSB="31" LSB="18"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
	</AddressSpace>
  </Processor>
<Config>
  <Option Name="Part" Val="xc7z030fbg676-2"/>
</Config>
</MemInfo>

 updatemem output:

updatemem -mode batch -meminfo data_rom.mmi -data test_rom.mem -proc /CPU/processing_system7_1 -bit system_top.bit -out output.bit -force -debug

****** updatemem v2017.3.1 (64-bit)
  **** SW Build 2035080 on Fri Oct 20 14:20:01 MDT 2017
  **** IP Build 2034413 on Fri Oct 20 15:56:25 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source C:/hwdt/Xilinx/Vivado/2017.3/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo data_rom.mmi -data test_rom.mem -proc /CPU/processing_system7_1 -bit system_top.bit -out output.bit -force -debug

Dump the BRAM Initialization Strings.
Loading bitfile system_top.bit
Loading data files...
Updating memory content...
Creating bitstream...
Writing bitstream output.bit...
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
update_mem completed successfully
update_mem: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 522.543 ; gain = 468.465
INFO: [Common 17-206] Exiting updatemem at Tue Feb  6 08:30:51 2018...

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