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Registered: ‎06-15-2017

Using SDK performance analysis to profile PL DDR3



Im putting a design together that uses DDR3 memory connected to the PL on a Zynq-7000 device.


I need to profile the performance of this memory (throughput and latency). I'd like to do this using the SDK performance analysis suite.


I've been successful so far in using an AXI traffic generator (ATG) and performance monitor (APM) connected to the MIG and PS7. I have the ATG configured for high level traffic with the "data" traffic profile. In the AXI address field (base and high) I enter the address allocated to the MIG in the block design address editor. I run the SDK Performance analysis suite with this design and I can see the expected throughput and latency in the APM counters window. 


Now for my problem:


I'd like to be able to configure the traffic throughput through SDK, as Ive seen done in xapp1219, 1202, ug1145. I've set the profile selection to "custom" and connected the S_AXI interface to the PS7 M_AXI_GP0. 


In the SDK performance analysis suite, I try to configure the traffic for my ATG in the ATG Configuration tab, however the only available start addresses are for the PS memory, i.e. PS DDR0-3 and OCM. I dont see how I configure my ATG through SDK, or where I provide the AXI address of my MIG, as I did for the "high level traffic" mode.


Any pointers are gratefully appreciated



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Registered: ‎02-26-2019

Has anybody solved this? I would be interested in the solution as well.

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