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Adventurer
Adventurer
8,945 Views
Registered: ‎01-13-2015

VDMA and AXI4-Stream to Video Out with no Locked signal

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Hi all,

 

I use VDMA and AXI4-Stream to Video Out.

But AXI4-Stream to Video Out does not assert Locked siganl and not send any output data.

 

I'm designing a VDMA pipeline.

The design is like TPG + VDMA + VTC + AXI4-Stream to Video Out : video and timing signals out on ZC702 Board.

For data path, all IPs use 20Mhz clock, and 10Mhz is used for AXI-Lite or to control peripherals.

VDMA's output send TPG's image data(3-byte:RGB) and I can see the data siganls via ILA(like chipscope) from the VDMA.

I use irregural video resolution: 60x40 ( this is for a test now), and I use VTC's custom setting, and VTC's mode is Master mode.

VDMA uses Dynamic-Master(write channel) and Dynamic-Slave(read channel).

In this design, AXI4-Stream to Video Out does not find out or catch out a synchronizing point between data from the VDMA and

timing signals from VTC. The IP does not assert not only Locked siganl but also Empty signal.

VTC generates proper signal for 60x40.

Sometimes, I can see a couple of Locked and Empty pluse signals, but output port does not send any data.

 

However, with other resolution like 352x288(smallest opion of VTC IP supports) works very well.

All the conditions and setting are same except the resolution size. Only the image size are different.

But when I use 352x288 works, but 60x40 does not works.

Is the Horizontal line too short to get a synchronized point??

 

Please give me any advices, and that might help me.

Even though 60x40 is for test but I have to make it up with this resolusion size..

 

Thank you...

 

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1 Solution

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Adventurer
Adventurer
17,289 Views
Registered: ‎01-13-2015

Re: VDMA and AXI4-Stream to Video Out with no Locked signal

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I think I found the problem.

VDMA should have enough frame buffer.

I have to VDMA 10s Frame buffer than AXI4-Stream to Video Out catchs up each frame and it sends Locked siganl and

no Empty siganl.

But I'm not 100% sure yet, beasue the image from TPG is not diplayed correctly. Now this is another issue now.

 

Should I check 'Allow Unaligned Transfers' for write and read channel??

 

For Genlock Mode, write channel is set as Dynamic-Master and read channel is set as Dynamic-Slave.

Both channel have no Fsync Options, and both Memory Map Data Width and Burst size is 32,

Stream data width is 24-bit(RGB color), and Line Buffer Depth is 1024.

 

 

 

Thank you...

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3 Replies
Xilinx Employee
Xilinx Employee
8,914 Views
Registered: ‎07-31-2012

Re: VDMA and AXI4-Stream to Video Out with no Locked signal

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Does resetting the core change anything when 60x40 fails? Can you attach the VTC core xci files and the other IP's XCI files if possible, this should give an idea if the settings are incorrect.

Also which version of Vivado is this?
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Highlighted
Adventurer
Adventurer
17,290 Views
Registered: ‎01-13-2015

Re: VDMA and AXI4-Stream to Video Out with no Locked signal

Jump to solution

I think I found the problem.

VDMA should have enough frame buffer.

I have to VDMA 10s Frame buffer than AXI4-Stream to Video Out catchs up each frame and it sends Locked siganl and

no Empty siganl.

But I'm not 100% sure yet, beasue the image from TPG is not diplayed correctly. Now this is another issue now.

 

Should I check 'Allow Unaligned Transfers' for write and read channel??

 

For Genlock Mode, write channel is set as Dynamic-Master and read channel is set as Dynamic-Slave.

Both channel have no Fsync Options, and both Memory Map Data Width and Burst size is 32,

Stream data width is 24-bit(RGB color), and Line Buffer Depth is 1024.

 

 

 

Thank you...

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Adventurer
Adventurer
8,874 Views
Registered: ‎01-13-2015

Re: VDMA and AXI4-Stream to Video Out with no Locked signal

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Hi 

 

How can I mark your reply as an answer,

 

And I have one more question. What is the way to calcurate a size of frame buffer for VDMA

I use Zync 7010 (Zybo board from Digilent), and this chip has its own DDR3 controller.

I refere XAPP1205 to design VDMA pipeline. I also have read other docmuments like datasheet of VDMA and XAPPs.

But I cannot see or find out a proper explanation to figure out the minimum number of frame buffer size.

 

Thank you...

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