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Adventurer
Adventurer
7,827 Views
Registered: ‎01-13-2015

VDMA and muti-clock domain

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Hi all,

 

I'm designing a VDMA pipe-line. In typical cases, AXIS_S2MM_ACLK and AXIS_MM2S_ACLK are same,

but I need using two different clocks. For example, TPG uses 200Mhz(as an input of VDMA), and AXI4-Stream to Video Out

(as ouput of VDMA) uses 148.5Mhz(HDMI 1080p). And AXI interconnect is used between VDMA and Zynq7 PS.

In this case, does this design work? I have tried all the possible ways that I can figure out, but it does not work.

Is there any ways to make this design to work?

 

Hopefully, someone can give me advices or comments.

 

Thank you..

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1 Solution

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Voyager
Voyager
15,059 Views
Registered: ‎04-21-2014

Re: VDMA and muti-clock domain

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On an axi interconnect, SY_ARESETN must be synchronous to SY_ACLK for a given Y.  Same for MX_ARESETN relative to MX_ACLK on the interconnect for a given X.  However, SY_ACLK doesn't need to be the same clock to MY_ACLK of the interconnect, or even ACLK/ARESETN

 

However, whatever is connected to the SY port of the interconnect, let's say M0_ of some other IP, both SY_ACLK and M0_ACLK needs to be the same clock (likewise for reset).

 

Likewise, whatever is connected to MZ of the interconnect, let's say S0_ of some other IP, both S0_ACLK and MZ_ACLK needs to be the same clock (likewise for reset).

 

The ACLK of the interconnect is the internal interconnect clock.  If ACLK, S00_ACLK, and M00_ACLK of the interconnect are all the same, the interconnect won't add clock domain crossing logic.

 

So, if you already understood this, can you upload a tcl of your .bd with the write_bd_tcl command?

 

If you didn't already understand this post, try to digest it first.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Voyager
Voyager
7,823 Views
Registered: ‎04-21-2014

Re: VDMA and muti-clock domain

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@emotaworld wrote:

 I have tried all the possible ways that I can figure out, but it does not work.


It would help us (me at least) understand the level of explanation required if you were more specific as to what you tried, and your thoughts on why it failed.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Adventurer
Adventurer
7,817 Views
Registered: ‎01-13-2015

Re: VDMA and muti-clock domain

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I refered Xilinx's reference desgin xapp1205. In this example, a Performance Monitor IP is used.

When I apply two different clocks ( as I mentnioned above), the monitor IP shows TX rate (size of transferred data), but

RX (received data ) shows 0.

 

When it works, both TX and RX shows some numbers, and those two numbers are almost same. In addition, 

monitor displays clear TPG through HDMI.

But different clocks are used, the monitor cannot display any image....

 

Than you..

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Voyager
Voyager
15,060 Views
Registered: ‎04-21-2014

Re: VDMA and muti-clock domain

Jump to solution

On an axi interconnect, SY_ARESETN must be synchronous to SY_ACLK for a given Y.  Same for MX_ARESETN relative to MX_ACLK on the interconnect for a given X.  However, SY_ACLK doesn't need to be the same clock to MY_ACLK of the interconnect, or even ACLK/ARESETN

 

However, whatever is connected to the SY port of the interconnect, let's say M0_ of some other IP, both SY_ACLK and M0_ACLK needs to be the same clock (likewise for reset).

 

Likewise, whatever is connected to MZ of the interconnect, let's say S0_ of some other IP, both S0_ACLK and MZ_ACLK needs to be the same clock (likewise for reset).

 

The ACLK of the interconnect is the internal interconnect clock.  If ACLK, S00_ACLK, and M00_ACLK of the interconnect are all the same, the interconnect won't add clock domain crossing logic.

 

So, if you already understood this, can you upload a tcl of your .bd with the write_bd_tcl command?

 

If you didn't already understand this post, try to digest it first.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Participant eewse
Participant
87 Views
Registered: ‎02-24-2019

Re: VDMA and muti-clock domain

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I got similar problem.

I want to so something below

hdmi in(frame:60Hz /pixel:142MHz) -> vdma 1(60Hz/142MHz) ->zynq -> vdma0(30Hz/71MHz) -> hdmi-out(30Hz/71MHz)

But whenever I set the pixel clock of vdma0 to 71MHz, hdmi out will be blank

 

Screenshot from 2019-07-06 15-25-48.png

Pls advise

 

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