VHDL code to access AXI interfaces

[bahne]

Hi,

the vivado will generate VHDL templates for AXI interfaces. I am looking for examples how to write the VHDL code to access the three different AXI interfaces. There is a comprehensive documentation on complex AXI interfaces, but where can I learn to build just a very simple interface.

Bahne

[htsvn]

Hi,

Are you trying to create your user IP with an AXI Interface?  If yes you can use "Create and Packaging IP Wizard"  page45 of

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_3/ug896-vivado-ip.pdf

--Hem

[bahne]

Hello Hem,

Thank you for your Answer. I was looking for the code, how to transfer data to and from AXI interfaces.

The

               AR#56609 (http://www.xilinx.com/support/answers/56609.htm) 

offered a template, but I was confused because the it requires so much code to establish a simple interface.

It would exactly meet my requirements, if I could have the files from

               xapp1168 (http://www.xilinx.com/support/documentation/application_notes/xapp1168-axi-ip-integrator.pdf)

in VHDL instead in verilog.

Bahne

[vemulad]

moving to embedded board

[chadigo]

Bahne, did you determine a solution? Did you just translate the verilog code? I'm in a similar situation, and I'm trying to look for an existing solution before creating my own...

[chadigo]

I was reading through UG896 that htsvn linked to. This is what I was trying to figure out, thanks! The wizard generates the VHDL code that acts as a template for implementing your custom function.

[emu]

So, any chance Xilinx starts to support the AXI interfaces in VHDL?

[apfelsaft]

Hi,

i'm in the same situation. Seaching for an AXI oder at least AXI-Lite VHDL Interface. For building my own VHDL Code  communication with MicroBlaze ( -> Ethernet).

Maybe Xilinx will put this on their record, for future dev..

Hopefully they will notice that their is interest, out there :-)

regards Apfelsaft

[goran]

Hi,

You can check the source code for some of the AXI peripherals that Xilinx provides in Vivado.

Not every IP is encrypted and it can give you a idea on how AXI interface is used.

Göran