01-17-2014 01:01 PM
the vivado will generate VHDL templates for AXI interfaces. I am looking for examples how to write the VHDL code to access the three different AXI interfaces. There is a comprehensive documentation on complex AXI interfaces, but where can I learn to build just a very simple interface.
01-17-2014 10:39 PM
Are you trying to create your user IP with an AXI Interface? If yes you can use "Create and Packaging IP Wizard" page45 of
01-19-2014 08:11 AM
Thank you for your Answer. I was looking for the code, how to transfer data to and from AXI interfaces.
offered a template, but I was confused because the it requires so much code to establish a simple interface.
It would exactly meet my requirements, if I could have the files from
in VHDL instead in verilog.
01-19-2014 11:18 PM
moving to embedded board
08-19-2014 08:27 AM
08-19-2014 08:41 AM
03-28-2016 11:35 PM
i'm in the same situation. Seaching for an AXI oder at least AXI-Lite VHDL Interface. For building my own VHDL Code communication with MicroBlaze ( -> Ethernet).
Maybe Xilinx will put this on their record, for future dev..
Hopefully they will notice that their is interest, out there :-)
04-03-2016 11:49 PM
You can check the source code for some of the AXI peripherals that Xilinx provides in Vivado.
Not every IP is encrypted and it can give you a idea on how AXI interface is used.