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patocarr
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Registered: ‎01-28-2008

Vitis 2020.1 templates missing on custom .xsa

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Hi folks,

  Importing a custom .xsa from Vivado into Vitis 2020.1 does not display software templates (i.e. hello world, lwIP echo server, etc.), only acceleration templates. But importing the ZCU102 .xsa does show the templates as expected.

  One thing I've noticed while selecting the platform on the New Application Project dialog, is that the ZCU102 shows as using a "Embedded SW Dev" flow, whereas my custom .xsa shows "DataCenter Accel". I'm assuming the difference stems from having the PS PCIe Endpoint enabled in the firmware.

  Is there any way to change this "flow" setting, or any other setting such that I can get access to the usual software templates from my custom .xsa platform? I've tried using baremetal as well as Linux with the same outcome, as shown in screenshot.

 

Thanks in advance for any insight,

-Pat

Screenshot 2020-08-08-12:46:38-New Application Project _01.png

 

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patocarr
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Hi folks,

  I have a response from Xilinx support regarding this case, with a workaround/solution. Setting the project property platform.uses_pr to 0 and then exporting the hardware (.xsa) fixes Vitis importing it as "Datacenter Accelerated", and properly identifying it as "Embedded SW Dev" platform type.

set_property platform.uses_pr 0 [current_project]

  Xilinx development will continue monitoring this case. In case you're curious, the service request is SR#10505629. I'd like to thank @kmorris for his support.

Thanks,

-Pat

 

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patocarr
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Hi folks,

  Here's the .xsa and screenshots showing the process that displays the issue.

- Open Vitis 2020.1

- Select Create new platform project, name it "DAQ16-post"

Screenshot 2020-08-09-12:15:42-New Platform Project _01.png

- Provide .xsa (attached as .zip). The design is on an RFSoC device with PS PCIe endpoint enabled.

- Select Standalone, psu_cortexa53_0, 64-bit, check Generate boot components. Finish.

Screenshot 2020-08-09-12:18:46-New Platform Project _01.png

- Once the platform is created, select File/New application project.

- Select the platform just created, DAQ16-post, and Next. Notice the "DataCenter Accel" flow.

Screenshot 2020-08-09-12:21:07-New Application Project _01.png

-  Give it a name, i.e. "hello"

Screenshot 2020-08-09-12:21:58-New Application Project _01.png

-  Select standalone_domain, and Next.

Screenshot 2020-08-09-12:22:44-New Application Project _01.png

- Verify no software templates shown, only SW acceleration templates.

Screenshot 2020-08-09-12:23:54-New Application Project _01.png

The Vitis IDE examples dialog displays only SW accelerated templates, which are downloaded on demand.

 

How can the SW templates be accessed? I don't need the SW accelerated examples.

 

Thanks in advance for any insight,

-Pat

 

 

 

 

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florentw
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Hi @patocarr 

The settings you are looking for have to be set in vivado.

First what is you end goal? are you looking to use v++? If not you need to select fixed platform when exporting the XSA (this would be like the previous SDK flow):

XSA.JPG


Florent
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patocarr
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Hi @florentw 

  I appreciate your response. The goal is to generate a "hello world" embedded example, to use to debug a larger issue regarding programming QSPI under 2020.1, to follow up on this post 

  I was sure I exported the hardware as "fixed" embedded platform, not "expandable". But just to make sure, I rebuilt the Vivado project and exported as you suggested.

Screenshot 2020-08-10-14:48:22-Export Hardware Platform_01.png

Screenshot 2020-08-10-14:48:32-Export Hardware Platform_01.png

Screenshot 2020-08-10-14:48:46-Export Hardware Platform_01.png

Screenshot 2020-08-10-14:48:53-Export Hardware Platform_01.png

 Then, on Vitis 2020.1, create a new platform project from scratch, importing the generated .xsa

Screenshot 2020-08-10-14:50:26-New Platform Project _01.png

 Then selecting New Application project, and selecting the platform, still reports "DataCenter Accel" flow:

Screenshot 2020-08-10-14:51:41-New Application Project _01.png

 I'm attaching the generated .xsa I used to test this. What's wrong with my process? I'm at a loss how to continue.

 

Thanks again!

-Pat

 

 

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florentw
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Hi @patocarr 

I can reproduce the issue with 2020.1. It sounds like a bug.

Would you be able to share your vivado design (I can share a link to our ftp server if needed) so I can do further test and see if it is still happening in 2020.2?

In the meantime, maybe try the following before generating the xsa as it might be a workaround:

set_property               platform.design_intent.embedded           true   [current_project]
set_property               platform.design_intent.server_managed    false   [current_project]
set_property               platform.design_intent.external_host     false   [current_project]
set_property               platform.design_intent.datacenter        false   [current_project]

Florent
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stephenm
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Yes, Florent is correct here. Vitis has a broader scope of use cases. So, we need to set the intent in the XSA file. By default it should be embedded. So, this might be a bug.

 

However, as Florent suggested, you can set these parameters in the Vivado TCL prior to creating the XSA.

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patocarr
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Hi folks @florentw @stephenm 

  Appreciate the support in this matter.

  I've tried setting the properties as workaround, re-generating the .xsa and recreating the platform project. The issue unfortunately persists, i.e. the platform is still seen as using the DataCenter Accel flow.

  The properties were undefined before being set, as shown below.

get_property platform.design_intent.datacenter [current_project]
undefined
get_property platform.design_intent.external_host [current_project]
undefined
get_property platform.design_intent.server_managed [current_project]
undefined
get_property platform.design_intent.embedded [current_project]
undefined
set_property               platform.design_intent.embedded           true   [current_project]
set_property               platform.design_intent.server_managed    false   [current_project]
set_property               platform.design_intent.external_host     false   [current_project]
set_property               platform.design_intent.datacenter        false   [current_project]

  While exporting the .xsa I notice 3 critical warnings related to PS PCIe. Not sure it's related, though it may need a new post. The attributes in question are properly set in the PCW.

write_hw_platform -fixed -include_bit -force -file /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16_top.xsa
INFO: [Vivado 12-4895] Creating Hardware Platform: /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16_top.xsa ...
INFO: [Hsi 55-2053] elapsed time for repository (/opt/Xilinx/Vivado/2020.1/data/embeddedsw) loading 0 seconds
CRITICAL WARNING: [Project 1-652] PCIeId Device attribute in the hardware design is empty.
CRITICAL WARNING: [Project 1-654] PCIeId Vendor attribute in the hardware design is empty.
CRITICAL WARNING: [Project 1-653] PCIeId Subsystem attribute in the hardware design is empty.
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16_top.xsa
write_hw_platform: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 9554.648 ; gain = 0.000 ; free physical = 469 ; free virtual = 64785

  @florentw I can upload this design to Xilinx FTP for testing. Please supply me with credential details at your convenience.

 

Thanks,

-Pat

 

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florentw
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Hi @patocarr 

I sent you a link to our ftp platform on your email address. Please use it to upload your project and I will look at it.

Regards,


Florent
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patocarr
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Hi @florentw 

  I've sent the project over EZ Move.

 

Thanks again for looking into this.

-Pat

 

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florentw
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Hi @patocarr 

Thank you for sending your project.

Unfortunately I cannot reproduce the issue on my machine (I will send you the xsa I have generated).

I have not changed anything in your project, just re-generated the BD/synthesis and implementation and the bitstream.

I will try without regenerating everything now 


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florentw
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HI @patocarr 

I tried your project without re-generating and I still get the Hello World template. This means that the settings of the vivado project are correct and this is not linked (at least not only) to the fact that you have a PCIe block in your design.

PS. To generate from vivado I tried with the following option

  • fixed -> pre-synthesis
  • fixed -> bitstream included

Can you do the following:

  • Make sure you are using the correct XSA and that a new XSA is correctly exported from Vivado
    • The best way is to remove the old XSA and use a new name for each xsa

Then FYI, I am working on a Linux RHEL 7.4 machine. I do not think the OS matter but if you or your colleague could try on a different machine (same OS or not) it might give a clue

Also try with the xsa I sent you just to make sure this is not coming from Vitis. 

I will be on holiday next week, but if you have any findings @stephenm can help further


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patocarr
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Hi @florentw 

  I appreciate the time you took to review this case. I hope you have a nice break. I have tested the .xsa you sent back with the same results, still shows as DataCenter Accel flow.

  I sent this file to a colleague to test on his OS (Ubuntu 18.04) with the same outcome. My OS is Fedora 31, which is not officially supported but works well, as it's a cutting edge RHEL and been using it for years. However, there's a few more tests we did that proves this OS is not at fault:

- Build a minimal test design on an RFSoC device with PS PCIe endpoint enabled on my Fedora system. This created the proper SW Embedded flow, showing the install is fine in this OS.

- My colleague's design also uses an RFSoC device with PS PCIe enabled, and it's a full design. On his OS, this created the proper flow. On my system, his .xsa also created the embedded flow. One thing to note, is that while creating the platform project, the list of processors shows a Microblaze entry, along with the RPU/APUs. We suspect it's the embedded instance in the PL DDR4 controller, however, my original design also has a [larger] PL DDR4 controller but no Microblaze shows up in the list.

  Comparing these two designs we find they're quite similar:

- Both have PL DDR4, though different widths/depths/parts.

- Both have Aurora instances, my design has 4 x4 instances; his has 2 x4.

- Both have the required PS configured as main controller for the RFDC IP and supporting logic.

- Both have PS PCIe endpoint enabled.

  The difference between them comes while creating the platform project, importing the .xsa, and how they are summarized as platforms, as shown in the screenshots below.

  In my design, the general info shows 9 DDR4 instances, 18 GB memory (!) and PCIe gen3x8, which is clearly wrong. It seems to imply I have a PL PCIe instance when there's none.

Screenshot 2020-08-14-13_11_16-New Application Project _01.png

  In his design, in contrast, there's no information about this and correctly states there's no acceleration resources available.

Screenshot 2020-08-14-13_12_38-New Application Project _01.png

  Obviously, this is all a mystery, and it's not clear what criteria the tool is using to get those differences when creating the platform projects from scratch. Perhaps you can see that from the project I have sent?

 

Thanks again,

-Pat

 

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patocarr
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Hi @stephenm @florentw 

  Well, I managed to get to the SW embedded templates using a slightly different approach. Instead of creating the platform project from scratch first, and then creating a new application project on top, I just created a new application project, creating the platform in the same process. Somehow this works, the templates are shown as expected. However, the platform project that is created shows the same characteristics as before, and creating other applications on top of it shows the same issue.

Let's create the new application project from the menu File/New/Application Project, then using the "Create a new platform from hardware" tab:

Screenshot 2020-08-14-14_16_11-New Application Project _01.png

Then give the application a name, and pick a APU:

Screenshot 2020-08-14-14_16_34-New Application Project _01.png

 Then create a new default standalone domain:

Screenshot 2020-08-14-14_16_48-New Application Project _01.png

 Then, voila, the SW templates for baremetal are shown:

Screenshot 2020-08-14-14_16_59-New Application Project _01.png

   By the way, picking the psu_cortexa53 SMP also correctly shows the Linux templates.

 As mentioned, once the app is created from the template, and the platform project is created from the .xsa, the platform still shows as DataCenter Accel when adding a new application, and the general info about the platform is also wrong, i.e. PCIe gen3x8.

Screenshot 2020-08-14-14_25_04-New Application Project _01.png

 So to summarize, there's something odd in this design/.xsa that triggers the wrong info when the platform is created, and because of this, the wrong SW templates are shown. Creating a new application from .xsa implicitly creates the platform project and somehow the baremetal templates are displayed. However, the platform created also displays the wrong information and thus other new applications when created won't benefit from the templates.

Thanks again for looking into this,

-Pat

 

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stephenm
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Can you ezmove me the updated XSA. Ill try this on Ubuntu.

There is a MB in the soft DDR used for calibration. However, this shouldn't show up in the list of processors.

Vitis uses the HSI commands under the hood to extract the metadata. For example

hsi::open_hw_design test.xsa

hsi::get_cells -filter {IP_TYPE==PROCESSOR}

 

 

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patocarr
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Hi @stephenm 

  The .xsa in question hasn't changed and it's in ezmove already; both actually, the one I first sent, and the one that @florentw re-built and sent back.

  Here's some more testing I've done using xsct and hsi, which look fine afaict, so the issue may be in Vitis itself.

[pcarr@storm vivado]$ xsct 
****** Xilinx Software Commandline Tool (XSCT) v2020.1
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
xsct% hsi::open_hw_design daq16/daq16_top.xsa                                        
INFO: [Hsi 55-2053] elapsed time for repository (/opt/Xilinx/Vitis/2020.1/data/embeddedsw) loading 0 seconds
hsi::open_hw_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1699.645 ; gain = 0.000 ; free physical = 2186 ; free virtual = 78221
daq16_top
xsct% set procs [hsi::get_cells -filter {IP_TYPE==PROCESSOR}]                        
psu_cortexa53_0 psu_cortexa53_1 psu_cortexa53_2 psu_cortexa53_3 psu_cortexr5_0 psu_cortexr5_1 psu_pmu_0
xsct% hsi::get_hw_designs                                                            
daq16_top
xsct% common::report_property [hsi::current_hw_design]                                                                                      
Property         Type     Read-only  Value
ADDRESS_TAG      string*  true       
BOARD            string   true       
CLASS            string   true       hw_design
DEVICE           string   true       xczu39dr
FAMILY           string   true       zynquplusRFSOC
NAME             string   true       daq16_top
PACKAGE          string   true       ffvf1760
PART             string   true       xczu39dr-ffvf1760-2-i
PATH             string   true       /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/axis_intcon.hwh
SPEEDGRADE       string   true       -2
SW_REPOSITORIES  string*  true       
TIMESTAMP        string   true       Mon Aug 10 13:31:53 2020
VIVADO_VERSION   string   true       2020.1
xsct% hsi::create_sw_design swdesign -proc psu_cortexa53_0 -os standalone                                                                   
swdesign                                                                                                                                    
xsct% common::report_property [hsi::current_sw_design]                                                                                      
Property            Type    Read-only  Value
APP_COMPILER        string  false      aarch64-none-elf-gcc
APP_COMPILER_FLAGS  string  false      
APP_LINKER_FLAGS    string  false      
BSS_MEMORY          string  false      
CLASS               string  true       sw_design
CODE_MEMORY         string  false      
DATA_MEMORY         string  false      
NAME                string  true       swdesign
PARTIAL             string  true       FALSE
xsct% hsi::get_drivers                                                                                                                      
axi_gpio_0 axi_gpio_1 axi_gpio_2 axi_intc_1 ddr4_0 mcdma_axi_intc_dma mcdma_axi_mcdma_0 psu_acpu_gic psu_adma_0 psu_adma_1 psu_adma_2 psu_adma_3 psu_adma_4 psu_adma_5 psu_adma_6 psu_adma_7 psu_afi_0 psu_afi_1 psu_afi_2 psu_afi_3 psu_afi_4 psu_afi_5 psu_afi_6 psu_ams psu_apm_0 psu_apm_1 psu_apm_2 psu_apm_5 psu_apu psu_cci_gpv psu_cci_reg psu_coresight_0 psu_crf_apb psu_crl_apb psu_csu_0 psu_csudma psu_ctrl_ipi psu_ddr_0 psu_ddr_phy psu_ddr_qos_ctrl psu_ddr_xmpu0_cfg psu_ddr_xmpu1_cfg psu_ddr_xmpu2_cfg psu_ddr_xmpu3_cfg psu_ddr_xmpu4_cfg psu_ddr_xmpu5_cfg psu_ddrc_0 psu_dp psu_dpdma psu_efuse psu_ethernet_1 psu_fpd_gpv psu_fpd_slcr psu_fpd_slcr_secure psu_fpd_xmpu_cfg psu_fpd_xmpu_sink psu_gdma_0 psu_gdma_1 psu_gdma_2 psu_gdma_3 psu_gdma_4 psu_gdma_5 psu_gdma_6 psu_gdma_7 psu_gpio_0 psu_iou_scntr psu_iou_scntrs psu_iousecure_slcr psu_iouslcr_0 psu_ipi_0 psu_lpd_slcr psu_lpd_slcr_secure psu_lpd_xppu psu_lpd_xppu_sink psu_mbistjtag psu_message_buffers psu_ocm psu_ocm_ram_0 psu_ocm_xmpu_cfg psu_pcie psu_pcie_attrib_0 psu_pcie_dma psu_pcie_high1 psu_pcie_high2 psu_pcie_low psu_pmu_global_0 psu_qspi_0 psu_qspi_linear_0 psu_r5_0_atcm_global psu_r5_0_btcm_global psu_r5_1_atcm_global psu_r5_1_btcm_global psu_r5_tcm_ram_global psu_rcpu_gic psu_rpu psu_rsa psu_rtc psu_sd_0 psu_serdes psu_siou psu_smmu_gpv psu_smmu_reg psu_ttc_0 psu_ttc_1 psu_ttc_2 psu_ttc_3 psu_uart_0 psu_usb_0 psu_usb_xhci_0 psu_wdt_0 psu_wdt_1 rf_dc rfdc_clocking_clk_adc rfdc_clocking_clk_dac system_management_wiz_0
xsct% common::report_property [hsi::get_os]                                                                                                 
Property                              Type    Read-only  Value
CLASS                                 string  true       os
CONFIG.clocking                       string  false      false
CONFIG.enable_sw_intrusive_profiling  string  false      false
CONFIG.hypervisor_guest               string  false      false
CONFIG.lockstep_mode_debug            string  false      false
CONFIG.microblaze_exceptions          string  false      false
CONFIG.predecode_fpu_exceptions       string  false      false
CONFIG.profile_timer                  string  false      none
CONFIG.sleep_timer                    string  false      none
CONFIG.stdin                          string  false      psu_uart_0
CONFIG.stdout                         string  false      psu_uart_0
CONFIG.ttc_select_cntr                string  false      2
CONFIG.zynqmp_fsbl_bsp                string  false      false
NAME                                  string  false      standalone
VERSION                               string  false      7.2
xsct% hsi::generate_app -app hello_world -proc psu_cortexa53_0 -dir app_out                                                                 
-- Build type:  Debug                                                                                                                       
-- Host:    Linux/x86_64
-- Target:  Generic/arm
-- Machine: zynqmp_a53
-- Looking for include file xintc.h
-- Looking for include file xintc.h - not found
-- Could NOT find Doxygen (missing:  DOXYGEN_EXECUTABLE) 
-- Looking for include file stdatomic.h
-- Looking for include file stdatomic.h - found
-- Configuring done
-- Generating done
-- Build files have been written to: /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/app_out/hello_world_bsp/psu_cortexa53_0/libsrc/libmetal_v2_1/build_libmetal
hsi::generate_app: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1699.645 ; gain = 0.000 ; free physical = 1149 ; free virtual = 77540

 

  So as mentioned, this xsct flow looks consistent with what SDK would [have] do[ne]. Not sure why Vitis reads the .xsa and decides it's a DataCenter Accel flow or gives memory and PCIe information that is wrong.

 

Thanks again for looking at this,

-Pat

 

PS: The ezmove link is https://ezmove.xilinx.com/human.aspx?r=439109141&arg12=msghistory&arg06=695096875&arg07=694988407

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stephenm
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Is it possible to ezmove the project? I want to start from scratch

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patocarr
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@stephenm 

The ezmove contains the original .xsa and the whole packaged project as well.

 

Thanks!

-Pat

 

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stephenm
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If I use the platforminfo -j <path to xpfm>.xpfm > dump.json command, I see that the intend here is set to data center

 

 

 

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patocarr
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Hi @stephenm 

  As a test, I have tried exporting the .xsa as "Expandable", as opposed to "Fixed" and it fails with the following message:

write_hw_platform -force -file /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16_expandable.xsa
INFO: [Vivado 12-4895] Creating Hardware Platform: /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16_expandable.xsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
ERROR: [BD 41-2088] No default platform clock is selected. Please set property is_default to true for one of the platform clocks
ERROR: [Project 1-1038] Failed to generate hpfm file for BD File: /home/pcarr/Work/Elk/DAQ/Firmware/DAQ16-2020.1/DDAQ4-Firmware/vivado/daq16/daq16.srcs/sources_1/bd/axis_ic_dmux/axis_ic_dmux.bd
ERROR: [Common 17-53] User Exception: Unable to get hpfm file from project property platform.hpfm_file or from the BD itself.

  I don't intend to export the platform to be used as "DataCenter Accel" nor I could, based on this output. The .xsa was exported as "Fixed" and somehow Vitis (or Vivado) gets confused and interprets it the wrong way.

  Based on the platforminfo command you shown, there's a chance Vivado is exporting the .xsa with the wrong info, or Vitis is importing it assuming something it's not. I really can't know from here.

  What I do know is that this design doesn't have 18 GB DDR and a PCIe Gen3 x8 instance, so that's clearly mistaken, and I suspect it's a hint to some translation error somewhere in the export/import process.

  Here's the same design exported as "Fixed" but without bitstream for ease of attachment size.

  In the attached .xsa, the xsa.json shows the same properties set in the project but all are false:

    "designIntent": {
        "dataCenter": {
            "value": "false",
            "explicit": "false"
        },
        "embedded": {
            "value": "false",
            "explicit": "false"
        },
        "externalHost": {
            "value": "false",
            "explicit": "false"
        },
        "serverManaged": {
            "value": "false",
            "explicit": "false"
        }
    },

  The properties in the project:

get_property platform.design_intent.datacenter [current_project]
false
get_property platform.design_intent.external_host [current_project]
false
get_property platform.design_intent.server_managed [current_project]
false
get_property platform.design_intent.embedded [current_project]
true

  So it looks like Vivado is not respecting these properties in the exported platform.

  I will upload the design to ezmove again, ensuring these properties were properly set.

 

Thanks again,

-Pat

 

 

 

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patocarr
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Hi @florentw 

  Did you have a chance to look at this issue after your break? I have uploaded more files to EZmove.

  Is it remotely possible to be related to this Petalinux-2020-1-vs-2019-2-QSPI-and-JTAG-boot post?

 

Thanks again for your insight.

-Pat

 

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florentw
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Hi @patocarr 

I am just getting back to this. Unfortunately I do not seems to be able to access any of the files you sent through EZmove. I thought we were keeping the files for 30 days but it seems to be less.

Let me try again with the XSA I have generated from your project.

I only tested creating the platform from the new application wizard. For some reason I thought this was what you were doing based on your explanations while I usually use the other flow (create and generate the platform first then create the application).

Regards


Florent
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Hi @patocarr 

@stephenm and I are able to reproduce the issue. We asked the development team and it seems to be a known issue which happens when PCIe is enabled that they are trying to fix for 2020.2.

The workaround that you have found (using create application wizard to create the platform) seems to be the best one at the moment. However, I am not exactly sure about the impact because even if you can still get the embedded templates, it seems that the platform is still set for Datacenter. So I am worried there can be some missing dependencies later in the flow. 

We are investigating further on this.


Florent
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patocarr
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Hi @florentw and @stephenm 

  I have waited for 2020.2 in anticipation for this issue to be fixed, but alas, it's still present. I have rebuilt the design in Vivado 2020.2 and imported it in Vitis 2020.2 with the same results. However, this design does not have PS PCIe or any PL PCIe enabled, and yet Vitis think it is DatacenterAccel type. Moreover, the platform information still shows the wrong values for number of DDRs, PCIe type and memory size, as shown in the screenshot.

  I have set these properties that were undefined and re-exported the .xsa, with the same results.

set_property platform.design_intent.embedded true [current_project ]
set_property platform.design_intent.datacenter false [current_project ]

 

Screenshot 2020-11-28-13_59_27-Selection_01.png

 Any information will be appreciated.

 

Thanks,

-Pat

 

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patocarr
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Hi,

  FYI, I have opened a Service Request to support, SR#10505629.

Thanks,

-Pat

 

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patocarr
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Hi, here's another data point related to Vivado exporting this design as .xsa. These attributes show as missing and throw critical warnings, as shown in screenshot:

Screenshot 2020-12-09-17_56_57-Export Hardware Platform_01.png

 Could this be related to the platform misidentified as Datacenter Accelerated? The PS PCIe is disabled... why are these attributes not set?

Thanks,

-Pat

 

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florentw
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Hi @patocarr 

Sorry I did not have time to reply. This was on my TODO list but I did not have time to get to it (this is not my main expertize). Good to know that you have a SR filed. This definitely need a fix


Florent
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patocarr
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Hi folks,

  I have a response from Xilinx support regarding this case, with a workaround/solution. Setting the project property platform.uses_pr to 0 and then exporting the hardware (.xsa) fixes Vitis importing it as "Datacenter Accelerated", and properly identifying it as "Embedded SW Dev" platform type.

set_property platform.uses_pr 0 [current_project]

  Xilinx development will continue monitoring this case. In case you're curious, the service request is SR#10505629. I'd like to thank @kmorris for his support.

Thanks,

-Pat

 

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patocarr
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Folks,

  Looking through the git log I see that a similar property was added in 2018.2 called dsa.uses_pr (among many other dsa.*) and this got apparently replaced by platform.uses_pr while upgrading to 2019.2.1. The git diff:

-set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
-set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
-set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
-set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
-set_property -name "dsa.emu_dir" -value "emu" -objects $obj
-set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
-set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
-set_property -name "dsa.flash_size" -value "1024" -objects $obj
-set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
-set_property -name "dsa.host_interface" -value "pcie" -objects $obj
-set_property -name "dsa.num_compute_units" -value "60" -objects $obj
-set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
-set_property -name "dsa.uses_pr" -value "1" -objects $obj
-set_property -name "dsa.vendor" -value "xilinx" -objects $obj
-set_property -name "dsa.version" -value "0.0" -objects $obj
+set_property -name "platform.uses_pr" -value "1" -objects $obj

 

Thanks,

-Pat

 

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