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Registered: ‎11-09-2019

Vitis build error on makefile

Hi,

I am trying to build a software project. I have imported .xsa file as a platform. The software build fails by showing below error.

make: *** [makefile:34: all] Error 2 blockDesignCon_projSW C/C++ Problem

make[1]: *** [src/subdir.mk:47: src/axiCommunication.o] Error 1

There are no errors in Vitis Log. How can I fix this?

Thanks.

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ibaie
Xilinx Employee
Xilinx Employee
497 Views
Registered: ‎10-06-2016

Hi nithinrngowda@gmail.com 

Are you still facing this issue? The posted log file does not provide too much information, if you are facing a build issue you need to check the Console output where the whole build process is logged.

Regards


Ibai
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