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Radhika_Jogleka
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Registered: ‎01-06-2021

Vitis build project error

I am facing following error while building the project in vitis. I want to perform read/write operations in IIC slave devices in zync ultasacele+ MPsoc.

I am trying to perform read/write operations in utility EEPROM(24AA256)

make: *** [Makefile:42: clean] Error 1

Invalid project path: Include path not found (C:\Users\user\Desktop\VLSI\project_12\eeprom_check\Debug).

 

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marcb
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Registered: ‎05-08-2012

Hi @Radhika_Jogleka 

Do the following references help related to a Makefile issue in Windows?

https://www.xilinx.com/support/answers/75536.html

https://forums.xilinx.com/t5/Embedded-Development-Tools/Vitis2020-2-running-custom-AXI-Lite-IP-makefile-gives-error/m-p/1194660#M57112

 

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