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KKilic
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Registered: ‎01-01-2021

Vitis can`t open hardware xsa if I use a simple custom AXI-Lite IP

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Hi,

I am developing an application for Zybo z20 and I have a basic hardware design with Zynq and a custom user IP. I just tried  Hello World application and it didnt compile.

The first error was "fatal error: xil_printf.h: No such file or directory" but then when I took a look at logs, I saw that Vitis was not able to import hardware file.

 

 

17:44:02 INFO	: Launching XSCT server: xsct.bat -n  -interactive C:\Projects\Vitis\WorkSpace\temp_xsdb_launch_script.tcl
17:44:04 INFO	: XSCT server has started successfully.
17:44:04 INFO	: plnx-install-location is set to ''
17:44:04 INFO	: Successfully done setting XSCT server connection channel  
17:44:04 INFO	: Platform repository initialization has completed.
17:44:04 INFO	: Successfully done setting workspace for the tool. 
17:44:04 INFO	: Successfully done query RDI_DATADIR 
17:44:50 INFO	: Result from executing command 'getProjects': BaseTester
17:44:50 INFO	: Result from executing command 'getPlatforms': 
17:44:50 WARN	: An unexpected exception occurred in the module 'platform project logging'
17:44:51 INFO	: Platform 'BaseTester' is added to custom repositories.
17:44:59 INFO	: Platform 'BaseTester' is added to custom repositories.
17:45:38 INFO	: Checking for BSP changes to sync application flags for project 'BaseTesterApp_Hello'...
17:45:39 ERROR	: Failed to openhw "C:/Projects/Vitis/WorkSpace/BaseTester/export/BaseTester/hw/BaseTester.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.

17:45:39 ERROR	: Failed to update application flags from BSP for 'BaseTesterApp_Hello'. Reason: null
java.lang.NullPointerException
	at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:305)
	at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:214)
	at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:61)
	at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
	at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
	at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
	at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
	at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
	at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)

 

 

If I take my custom IP  out of design, it works. The point I don`t understand is, I created my custom IP with Vivado  wizard (AXI Lite IP)  and haven`t made any change. I was just testing how to create and access to AXI registers. So there is no custom verilog code in the IP.  No synthesis or implementation error either.

temp1.png

 

any idea?

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KKilic
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Registered: ‎01-01-2021
9 Replies
joancab
Teacher
Teacher
1,226 Views
Registered: ‎05-11-2015

"vivado wizard", do you mean with "Create and Package new IP"? Did you export hw with bitstream in both cases? One possible reason that comes to my mind is  maybe the empty (unconnected) AXI slave port.

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KKilic
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Registered: ‎01-01-2021

yes, I used "create and Package new IP". Without changing anything I just add it to block diagram.

AXI slave is connected to AXI connector which is connected to Zynq.

 

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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

I'm suspicious of an empty AXI, could you add some dummy code to it?

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KKilic
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Registered: ‎01-01-2021

Yes I did. At first it had a simple code , just reading a register and turning on a led but didn`t work. So I thought, I made a mistake. Took out IP and Vitis compiled perfectly. So the problem was IP. Then I just put an empty AXI IP, but problem was still exist. 

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KKilic
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tcs6770
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986 Views
Registered: ‎09-14-2018

I observe the same problem with a Zybo-Z7-20 board when adding a custom AXI IP peripheral to a Vivado project in 2020.2. 

To reproduce it, I start with a working Zynq block design and then add a custom IP peripheral.  For my example I did the LED_controller example from the Zynq book tutorial.  For some reason the problem seems to only occur when the custom AXI IP is an AXI-lite device.  If I make the AXI IP a stream device, I have no problems when exporting the hardware .xsa file. But with a custom AXI lite block, the Vitis IDE will no longer build.  The proposed (make clean) solution did not work for me.  

The following VITIS log error always presents; 

12:42:00 INFO : Checking for BSP changes to sync application flags for project ..
12:42:00 ERROR : Failed to openhw "C:/Users/tsmit/workspace/system_wrapper/export/system_wrapper/hw/system_wrapper.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.

I can then archive the Vivado project with the custom AXI-lite peripheral to a Ubuntu VM, rerun the vivado project, export hardware and everything builds fine in Vitis on Linux. 

Can anyone else confirm this on Vivado 2020.2, Vitis 2020.2, and the Zynq device family?  Any help would be much appreciated...

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KKilic
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Registered: ‎01-01-2021

Did you try changing makefile as described in the solution?

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tcs6770
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Registered: ‎09-14-2018

I updated the make file per the solution posted (https://forums.xilinx.com/t5/Embedded-Development-Tools/Problem-in-Vitis-2020-1-bsp-build/td-p/1142282). 

There seemed to be a couple suggestions regarding changing { to ( in the OBJECTS section.   Nothing seemed to work.

On my Ubuntu 18.04 VM everything compiles and programs correctly so I have migrated my development to there for now. What sucks is in Hyper-V you cant easily share USB devices so I have to use VirtualHere to share the ZYBO USB-JTAG over the network.

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KKilic
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Registered: ‎01-01-2021

This solution worked for me.

https://www.xilinx.com/support/answers/75527.html

Yes I think it is something about Windows.

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